- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄140359 > WEDPN16M64VR-66BM (MICROSEMI CORP-PMG MICROELECTRONICS) 16M X 64 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 PDF資料下載
參數(shù)資料
| 型號(hào)： | WEDPN16M64VR-66BM |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 16M X 64 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大?。?/td> | 423K |
| 代理商： | WEDPN16M64VR-66BM |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPN16M64VR-XBX
8
the row will remain open for subsequent accesses. Read data
appears on the I/Os subject to the logic level on the DQM
inputs two clocks earlier. If a given DQM signal was registered
HIGH, the corresponding I/Os will be High-Z two clocks later;
if the DQM signal was registered LOW, the I/Os will provide
valid data.
WRITE
The WRITE command is used to initiate a burst write access
to an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-8 selects the
starting column location. The value on input A10 determines
whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE
is selected, the row being accessed will be precharged at the
end of the WRITE burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses. Input data
appearing on the I/Os is written to the memory array subject
to the DQM input logic level appearing coincident with the
data. If a given DQM signal is registered LOW, the correspond-
ing data will be written to memory; if the DQM signal is
registered HIGH, the corresponding data inputs will be
ignored, and a WRITE will not be executed to that byte/
column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued.
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above, without
requiring an explicit command. This is accomplished by using
A10 to enable AUTO PRECHARGE in conjunction with a
specific READ or WRITE command. A precharge of the bank/
row that is addressed with the READ or WRITE command is
automatically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
AUTO PRECHARGE does not apply. AUTO PRECHARGE is
nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit PRECHARGE
command was issued at the earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered
READ or WRITE command prior to the BURST TERMINATE
command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in
conventional DRAMs. This command is nonpersistent, so it
must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller.
This makes the address bits “Don’t Care” during an AUTO
REFRESH command. Each 256Mb SDRAM requires 8,192
AUTO REFRESH cycles every refresh period (tREF). Providing
a distributed AUTO REFRESH command will meet the refresh
requirement and ensure that each row is refreshed. Alterna-
tively, 8,192 AUTO REFRESH commands can be issued in a
burst at the minimum cycle rate (tRC), once every refresh
period (tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data in the
SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is
initiated like an AUTO REFRESH command except CKE is
disabled (LOW). Once the SELF REFRESH command is regis-
tered, all the inputs to the SDRAM become “Don’t Care,” with
the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its
own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh mode
for a minimum period equal to tRAS and may remain in self
refresh mode for an indefinite period beyond that.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WE128K8-300CC | EEPROM 5V MODULE, CDIP32 |
| W25Q16CVDAAP | 16M X 1 SPI BUS SERIAL EEPROM, PDIP8 |
| WE-128K32-200HI | 512K X 8 EEPROM 5V MODULE, 200 ns, CPGA66 |
| WE128K16-300CC | 128K X 16 EEPROM 5V MODULE, 300 ns, CDMA40 |
| WS512K32F-25H2QA | 2M X 8 MULTI DEVICE SRAM MODULE, 25 ns, CHMA66 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN16M64VR-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx64 REGISTERED SYNCHRONOUS DRAM |
| WEDPN16M64VR-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Registered SDRAM MCP |
| WEDPN16M64V-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx64 Synchronous DRAM |
| WEDPN16M64V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WEDPN16M72V-100B2C | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:16Mx72 Synchronous DRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。