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參數(shù)資料
| 型號： | WED416S8030A10SI |
| 英文描述： | 2Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,2M x 16 位 x 4 組同步動態(tài)RAM) |
| 中文描述： | 2Mx 16位× 4個銀行同步DRAM（100MHz時，2分× 16位× 4個組同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 354K |
| 代理商： | WED416S8030A10SI |
WED416S8030A
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
DESCRIPTION
The WED416S8030A is 134,217,728 bits of synchronous high data
rate DRAM organized as 4 x 2,097,152 words x 16 bits. Synchronous
design allows precise cycle control with the use of systemclock,
I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable burst lengths and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
Available in a 54 pin TSOP type II package the WED416S8030A is
tested over the industrial temp range (-40
°
C to +85
°
C) providing
a solution for rugged main memory applications.
2M x 16 Bits x 4 Banks Synchronous DRAM
FEATURES
I
Single 3.3V power supply
I
Fully Synchronous to positive Clock Edge
I
Clock Frequency = 100, 83MHz
I
SDRAM CAS Latency = 3 (100MHz), 2 (83MHz)
I
Burst Operation
Sequential or Interleave
Burst length = programmable 1,2,4,8 or full page
Burst Read and Write
Multiple Burst Read and Single Write
I
DATA Mask Control per byte
I
Auto Refresh (CBR) and Self Refresh
4096 refresh cycles across 64ms
I
Automatic and Controlled Precharge Commands
I
Suspend Mode and Power Down Mode
I
Industrial Temperature Range
FIG. 1
PIN DESCRIPTION
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
V
SS
NC/RFU
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
V
DD
LDQM
WE
CAS
RAS
CE
BA
0
BA
1
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
T
(
J une 2000 Rev. 0
ECO#12861
A
0-11
Address Inputs
BA
0,
BA
1
Bank Select Addresses
CE
Chip Select
WE
Write Enable
CLK
Clock Input
CKE
Clock Enable
DQ
0-15
Data Input/Output
L(U)DQM
Data Input/Output Mask
RAS
Row Address Strobe
CAS
Column Address Strobe
V
DD
Power (3.3V)
V
DDQ
Data Output Power
V
SS
Ground
V
SSQ
Data Output Ground
NC
No Connection
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| WED48S8030E | Industrial SDRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED416S8030A12SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2Mx16x 4 Banks Synchronous DRAM |
| WED416S8030A-SI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial SDRAM |
| WED48S8030E | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2M x 8 Bits x 4 Banks Synchronous DRAM |
| WED48S8030E10SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2M x 8 Bits x 4 Banks Synchronous DRAM |
| WED48S8030E8SI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2M x 8 Bits x 4 Banks Synchronous DRAM |
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