參數(shù)資料
型號: WED48S8030E
英文描述: Industrial SDRAM
中文描述: 工業(yè)內(nèi)存
文件頁數(shù): 1/26頁
文件大?。?/td> 1683K
代理商: WED48S8030E
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED48S8030E
February 2002 Rev. 2
ECO #14194
2M x 8 Bits x 4 Banks Synchronous DR
AM
DESCRIPTION
The WED48S8030E is 67,108,864 bits of synchronous high
data rate DRAM organized as 4 x 2,097,152 words x 8 bits.
Synchronous design allows precise cycle control with the
use of system clock, I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Available in a 54 pin TSOP type II package the WED48S8030E
is tested over the industrial temp range (-40C to +85C) pro-
viding a solution for rugged main memory applications.
FEATURES
Single 3.3V power supply
Fully Synchronous to positive Clock Edge
Clock Frequency = 125, 100MHz
SDRAM CAS Latency = 2
Burst Operation
Sequential or Interleave
Burst length = programmable 1,2,4,8 or full page
Burst Read and Write
Multiple Burst Read and Single Write
DATA Mask Control
Auto Refresh (CBR) and Self Refresh
4096 refresh cycles across 64ms
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
Industrial Temperature Range
P
IN
C
ONFIGURATION
FIG. 1
P
IN
D
ESCRIPTION
A
0-11
BA
0
, BA
1
CE
WE
CLK
CKE
DQ
0-7
DQM
RAS
CAS
V
DD
V
DDQ
V
SS
V
SSQ
NC
Address Inputs
Bank Select Addresses
Chip Select
Write Enable
Clock Input
Clock Enable
Data Input/Output
Data Input/Output Mask
Row Address Strobe
Column Address Strobe
Power (3.3V)
Data Output Power
Ground
Data Output Ground
No Connection
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