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參數(shù)資料
| 型號： | WED2ZL361MS30BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 3 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 645K |
| 代理商： | WED2ZL361MS30BC |
3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
WED2ZL361MS
Oct, 2002
Rev. 5
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
WRITE TRUTH TABLE
CEx# ADV WE# BWx# OE# CKE# CK Address Accessed
Operation
H
L
X
L
↑
N/A
Deselect
X
H
X
L
↑
N/A
Continue Deselect
L
H
X
L
↑
External Address
Begin Burst Read Cycle
X
H
X
L
↑
Next Address
Continue Burst Read Cycle
L
H
X
H
L
↑
External Address
NOP/Dummy Read
X
H
X
H
L
↑
Next Address
Dummy Read
L
X
L
↑
External Address
Begin Burst Write Cycle
X
H
X
L
X
L
↑
Next Address
Continue Burst Write Cycle
L
H
X
L
↑
N/A
NOP/Write Abort
X
H
X
H
X
L
↑
Next Address
Write Abort
X
H
↑
Current Address
Ignore Clock
NOTES:
1.
X means “Don’t Care.”
2.
The rising edge of clock is symbolized by (
↑ )
3.
A continue deselect cycle can only be entered if a deselect cycle is executed rst.
4.
WRITE# = L means Write operation in WRITE TRUTH TABLE.
WRITE# = H means Read operation in WRITE TRUTH TABLE.
5.
Operation nally depends on status of asynchronous input pins (ZZ and OE#).
6.
CEx# refers to the combination of CE1#, CE2 and CE2#.
WE# BWa# BWb# BWc# BWd#
Operation
H
X
Read
L
H
Write Byte a
L
H
L
H
Write Byte b
L
H
L
H
Write Byte c
L
H
L
Write Byte d
L
Write All Bytes
L
H
Write Abort/NOP
NOTES:
1.
X means “Don’t Care.”
2.
All inputs in this table must meet setup and hold time around the
rising edge of CK (
↑ ).
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