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參數資料
| 型號： | WED2DL36514AV35BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 3.5 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數： | 12/12頁 |
| 文件大小： | 266K |
| 代理商： | WED2DL36514AV35BC |
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White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL36513V
WED2DL36513AV
FIG. 4 WRITE TIMING DIAGRAM
ADSP
ADSC
ADDRESS
BWx
CE
(NOTE 2)
tADSS
tADSH
ADV
OE
CLOCK
A2
A1
tAS
tAH
Q
tAAS
tAAH
tKH
tKL
tKC
tOEHZ
BURST READ
SINGLE WRITE
BURST WRITE
Extended BURST WRITE
(NOTE 5)
A3
DON’T CARE
UNDEFINED
(NOTE 3)
ADV suspends burst
tCSS
tCSH
tWS
tWA
ADSC extends burst
BYTE WRITE signals are ignored for
first cycle when ADSP initiates burst.
(NOTE 1)
D
D(A1)
D(A2)
D(A2+1)
D(A2+2)D(A2+3)D(A3)D(A3+1)
HIGH-Z
tADSS
tADSH
GW
tWH
(NOTE 3)
(NOTE 5)
tWS
(NOTE 4)
D(A3+2)
tDS tDH
NOTES:
1. D (A2) refers to output from address A2. D (A2+1) refers to output from the next internal burst address following A2.
2. CE2 and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and
CE2 is LOW.
3. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contentin for the
time period prior to the byte write enable inputs being sampled.
4. ADV must be HIGH to permit a WRITE to the load address.
5. Full-width WRITE can be initiated by GW LOW, or GW HIGH and BWE, BWa, - BWd LOW. Timing is shown assuming that the device was not
enabled before entering into its sequence. OE does not cause Q to be driven until after the following clock rising edge.
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