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參數(shù)資料
| 型號(hào)： | WED2DL36514AV35BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 STANDARD SRAM, 3.5 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | WED2DL36514AV35BC |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2DL36513V
WED2DL36513AV
October 1999 Rev. 2
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-
power CMOS designs that are fabricated using an advanced
CMOS process. WEDC’s 16Mb SyncBurst SRAMs integrate two
512K x 18 SRAMs into a single BGA package to provide 512K x
36 configuration. All synchronous inputs pass through registers
controlled by a positive - edge-triggered single-clock input (CLK).
The synchronous inputs include all addresses, all data inputs,
active LOW chip enable (CE), burst control inputs (ADSC, ADSP,
ADV), byte write enables (BW0-3) and global write (GW). Asyn-
chronous inputs include the output enable (OE), clock (CLK) and
snooze enable (ZZ). There is also a burst mode input (MODE) that
selects between interleaved and linear burst modes. Write Cycles
can be from one to four bytes wide, as controlled by the write
control inputs. Burst operation can be initiated with either address
status processor (ADSP) or address status controller (ADSC)
inputs. Subsequent burst addresses can be internally generated
as controlled by the burst advance input (ADV).
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
512Kx36 Synchronous Pipeline Burst SRAM PRELIMINARY*
FEATURES
s Fast clock speed: 200, 166, 150 & 133MHz
s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
s Available with 1.5ns setup and 0.5ns hold times or 1.0ns setup
and hold times.
s Single +3.3V power supply (VDD)
s Seperate +3.3V or +2.5V isolated output buffer supply (VDDQ)
s Snooze Mode for reduced-power standby
s Single-cycle deselect
s Common data inputs and data outputs
s Individual Byte Write control and Globa Write
s Clock-controlled and registered addresses, data I/Os and
control signals
s Burst control (interleaved or linear burst)
s Packaging:
119-bump BGA package
s Low capacitive bus loading
s Available in either single CE or three CE configuration
s IEEE 1149.1 JTAG Compatible Boundary Scan (available on
single CE version only)
FIG. 1
BLOCK DIAGRAM
PIN CONFIGURATION
(TOP VIEW)
123
4
5
67
A
VDDQ
SA
ADSP
SA
VDDQ
B
NC
SA
ADSC
SA
NC
C
NC
SA
VDD
SA
NC/CE2*
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
VSS
CE
VSS
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
BWc
ADV
BWb
DQb
H
DQc
VSS
GW
VSS
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
VSS
CLK
VSS
DQa
L
DQd
BWd
NC
BWa
DQa
M
VDDQ
DQd
VSS
BWE
VSS
DQa
VDDQ
N
DQd
VSS
SA1
VSS
DQa
P
DQd
DQPd
VSS
SA0
VSS
DQPa
DQa
R
NC
SA
MODE
VDD
NC
SA
NC/CE2*
T
NC
SA
NC
ZZ
U
VDDQ
TMD
TDI
TCK
TDO
NC
VDDQ
DQb, DQPb
DQa, DQPa
GW
ADV
SA
CLK
ADSP
ADSC
OE
BWE
CE
MODE
ZZ
BWa
BWb
512K x 18
SSRAM
DQd, DQPd
DQc, DQPc
512K x 18
SSRAM
BWc
BWd
* Enable on pins C7 and R7 are options for the three CE density only.
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