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參數(shù)資料
| 型號(hào)： | WE128K32-300G2TME |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 300 ns, CQFP68 |
| 封裝： | 22.40 X 22.40 MM, 4.57 MM HEIGHT, HERMETIC SEALED, CERAMIC, LQFP-68 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | WE128K32-300G2TME |
5
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
WE128K32-XG2TXE
AC READ CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
READ
The WE128K32-XG2TXE stores data at the memory location
determined by the address pins. When CS and OE are low and
WE is high, this data is present on the outputs. When CS and
OE are high, the outputs are in a high impedance state. This
two line control prevents bus contention.
Read Cycle Parameter
Symbol
-150
-200
-250
-300
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
150
200
250
300
ns
Address Access Time
tACC
150
200
250
300
ns
Chip Select Access Time
tACS
150
200
250
300
ns
Output Hold from Add. Change, OE or CS
tOH
0000
ns
Output Enable to Output Valid
tOE
10
75
10
75
10
85
10
85
ns
Chip Select or OE to High Z Output
tDF
55
70
ns
RESET Low to Output Float
tDFR
350
ns
RESET to Output Delay
tRR
450
ns
FIG. 5
READ WAVEFORMS
t
ADDRESS
CS
OE
OUTPUT
OH
tDF
tACC
t RC
tOE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
RESET
tDFR
tRR
NOTES:
OE may be delayed up to tACS - tOE after the
falling edge of CS without impact on tOE or by
tACC - tOE after an address change without
impact on tACC.
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