參數(shù)資料
型號： W9812G6DH-8H
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝： 0.400 INCH, 0.80 MM PITCH, ROHS COMPLIANT, TSOP2-54
文件頁數(shù)： 9/44頁
文件大?。?/td> 1221K
代理商： W9812G6DH-8H
W981216DH/ W9812G6DH
Publication Release Date: June 6, 2005
- 17 -
Revision A08
12.16 Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at
the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once
the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the
SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled.
The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits
Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC
cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
12.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
12.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the
clock. A No Operation Command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
12.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.
12.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W9812G6GH 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M X 4 BANKS X 16 BITS SDRAM
W9812G6GH-6 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M X 4 BANKS X 16 BITS SDRAM
W9812G6GH-6C 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M X 4 BANKS X 16 BITS SDRAM
W9812G6GH-6I 制造商:WINBOND 制造商全稱:Winbond 功能描述:2M X 4 BANKS X 16 BITS SDRAM
W9812G6GH-75 制造商:Winbond Electronics Corp 功能描述:8M * 16 SDRAM
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