參數(shù)資料
型號: W921C400
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 35/53頁
文件大小: 394K
代理商: W921C400
W921E400A/W921C400
Publication Release Date: July 1999
- 35 -
Revision A3
STPRF register: (address = 035H, default data = 8H)
b3
b2
b1
b0
0: Stop released by INT0 (P4.3) is disable
1: Stop released by INT0 (P4.3) is enable
0: Stop released by any pin of PB is disable
1: Stop released by any pin of PB is enable
0: Stop released by P4.2 is disable
1: Stop released by P4.2 is enable
0: Stop released by any pin of PA is disable
1: Stop released by any pin of PA is enable
When stop mode is active, if the stop condition release flag(STPRF) is set before the STOP
instruction is executed, the low level signal on the P4, PA or PB ports will release the stop mode and
a delay of 256 machine cycles occurs right aftr the stop mode is released, then the next instruction is
executed or the program counter(PC) jumps to interrupt subroutine if the interrupt is enable and
interrupt request exists.
The control flow chart is shown below:
Stop mode operation flow chart
START
STOP
Enter STOP Mode
INT Enable
Yes
No
INT Vector
RTNI
PC
PC + 1
STOP
No
Yes
(Only falling signal on
INT0 or P4.2)
(PA, PB Ports on
low level state)
System will Delay 256
Machine Cycle
Automatically
Next
Instruction
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