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參數(shù)資料
| 型號： | W78M64110SBI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 8M X 64 FLASH 3.3V PROM, 110 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 6/50頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | W78M64110SBI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M64VP-XSBX
November 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 10
White Electronic Designs Corp. reserves the right to change products or specications without notice.
HARDWARE DATA PROTECTION
METHODS
The device offers two main types of data protection at the
sector level via hardware control:
When WP#/ACC is at VIL, the either the highest or
lowest sector is locked (device specic).
There are additional methods by which intended or
accidental erasure of any sectors can be prevented via
hardware means. The following subsections describes
these methods:
WP#/ACC METHOD
The Write Protect feature provides a hardware method of
protecting one outermost sector. This function is provided
by the WP#/ACC pin and overrides the previously discussed
Sector Protection/Unprotection method.
If the system asserts VIL on the WP#/ACC pin, the device
disables program and erase functions in the highest or
lowest sector independently of whether the sector was
protected or unprotected using the method described in
Advanced Sector Protection/Unprotection.
If the system asserts VIH on the WP#/ACC pin, the device
reverts to whether the boot sectors were last set to be
protected or unprotected. That is, sector protection or
unprotection for these sectors depends on whether they
were last protected or unprotected.
The WP#/ACC pin must be held stable during a command
sequence execution. WP# has an internal pull-up; when
unconnected, WP# is set at VIH.
NOTE
If WP#/ACC is at VIL when the device is in the standby mode,
the maximum input load current is increased.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets to
reading array data. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the proper
signals to the control inputs to prevent unintentional writes
when VCC is greater than VLKO.
WRITE PULSE “GLITCH PROTECTION”
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
POWER-UP WRITE INHIBIT
If WE# = CE# = RESET# = VIL and OE# = VIH during power
up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
POWER CONSERVATION MODES
STANDBY MODE
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed
in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE#
and RESET# inputs are both held at VCC ± 0.3 V. The device
requires standard access time (tCE) for read access, before
it is ready to read data. If the device is deselected during
erasure or programming, the device draws active current
until the operation is completed. ICC4 in “DC Characteristics”
represents the standby current specication
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC + 30 ns. The
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available
to the system. ICC6 represents the automatic sleep mode
current specication.
HARDWARE RESET# INPUT
OPERATION
The RESET# input provides a hardware method of resetting
the device to reading array data. When RESET# is driven
low for at least a period of tRP, the device immediately
terminates any operation in progress, tristates all outputs,
and ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state
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