參數(shù)資料
型號(hào)： W78M32VP110BC
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： PROM
英文描述： 8M X 32 FLASH 3.3V PROM, 110 ns, PBGA159
封裝： 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159
文件頁數(shù)： 2/51頁
文件大小： 1637K
代理商： W78M32VP110BC
10
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M32VP-XBX
January 2010
Rev. 12
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DQ5: EXCEEDED TIMING LIMITS
DQ5 indicates whether the program or erase time has
exceeded a specied internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed. The device
does not output a 1 on DQ5 if the system tries to program a
1 to a location that was previously programmed to 0. Only
an erase operation can change a 0 back to a 1. Under this
condition, the device ignores the bit that was incorrectly
instructed to be programmed from a 0 to a 1, while any
other bits that were correctly requested to be changed from
1 to 0 are programmed. Attempting to program a 0 to a 1
is masked during the programming operation. Under valid
DQ5 conditions, the system must write the reset command
to return to the read mode (or to the erase-suspend-read
mode if a sector was previously in the erase-suspend-
program mode).
DQ3: SECTOR ERASE TIMEOUT STATE
INDICATOR
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not erasure
has begun. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected
for erasure, the entire time-out also applies after each
additional sector erase command. When the time-out period
is complete, DQ3 switches from a “0” to a “1.” If the time
between additional sector erase commands from the system
can be assumed to be less than tSEA, then the system
need not monitor DQ3. See Sector Erase for more details.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted the
command sequence, and then read DQ3. If DQ3 is “1,”
the Embedded Erase algorithm has begun; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the device
accepts additional sector erase commands. To ensure
the command has been accepted, the system software
should check the status of DQ3 prior to and following each
sub-sequent sector erase command. If DQ3 is high on the
second status check, the last command might not have
been accepted. Table 18 shows the status of DQ3 relative
to the other status bits.
DQ1: WRITE TO BUFFER ABORT
DQ1 indicates whether a Write to Buffer operation was
aborted. Under these conditions DQ1 produces a “1”.
The system must issue the “Write to Buffer Abort Reset”
command sequence to return the device to reading array
data. See Write Buffer Programming for more details.
WRITING COMMANDS/COMMAND
SEQUENCES
During a write operation, the system must drive CE# and
WE# to VIL and OE# to VIH when providing an address,
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the 1st
rising edge of WE# or CE#. An erase operation can erase
one sector, multiple sectors, or the entire device. Table 1
indicate the address space that each sector occupies. The
device address space is divided into uniform 64KW/128KB
sectors. A sector address is the set of address bits required
to uniquely select a sector. ICC2 in “DC Characteristics”
represents the active current specication for the write
mode. “AC Characteristics” contains timing specication
tables and timing diagrams for write operations.
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in progress or
complete. The RY/BY# status is valid after the rising edge of
the nal WE# pulse in the command sequence. Since RY/
BY# is an open-drain output, several RY/BY# pins can be
tied together in parallel with a pull-up resistor to VCC. This
feature allows the host system to detect when data is ready
to be read by simply monitoring the RY/BY# pin, which is a
dedicated output and controlled by CE# (not OE#).
HARDWARE RESET
The RESET# input provides a hardware method of resetting
the device to reading array data. When RESET# is driven
low for at least a period of tRP (RESET# Pulse Width), the
device immediately terminates any operation in progress,
tristates all outputs, resets the conguration register, and
ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state
machine to reading array data.
To ensure data integrity Program/Erase operations that were
interrupted should be reinitiated once the device is ready to
accept another command sequence.
When RESET# is held at VSS, the device draws VCC reset
current (ICC5). If RESET# is held at VIL, but not at VSS, the
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