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參數(shù)資料
| 型號(hào)： | W78IE54P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MTP MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 211K |
| 代理商： | W78IE54P |
Preliminary W78IE54
Publication Release Date: August 1999
- 9 -
Revision A1
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78IE54 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ON-CHIP MTP ROM CHARACTERISTICS
The W78IE54 has several modes to program the on-chip MTP-ROM. All these operations are
configured by the pins RST, ALE, PSEN, A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE(P3.6), OE(P3.7), A0(P1.0) and V
PP
(EA ). Moreover, the A15
A0(P2.7
P2.0,
P1.7
P1.0) and the D7
D0(P0.7
P0.0) serve as the address and data bus respectively for these
operations.
Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
Output Disable Condition
When the OE is set to high, no data output appears on the D7... D0.
Program Operation
This operation is used to program the data to MTP ROM and the security bits. Program operation is
done when the Vpp is reach to Vcp (12.5V) level, CE set to low, and OE set to high.
Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the MTP
ROM cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to
Vep level, CE set to low, and OE set to high.
Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if Vpp = Vep(14.5V), CE is high and
OE is low.
Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6(CE) = V
IH
, P3.7(OE) = V
IH
, erasing or programming of non-targeted chips is inhibited. So,
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
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