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參數(shù)資料
| 型號： | W78IE54P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MTP MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 211K |
| 代理商： | W78IE54P |
Preliminary W78IE54
Publication Release Date: August 1999
- 11 -
Revision A1
B0
B1
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Registers
Company ID (#DAH)
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
1
1
0
1
0
Device ID (#61H)
0
1
1
0
1
0
0
Security Bits
0
16KB MTP ROM
Program Memory
Reserved
Security Register
0FFFFh
0000h
3FFFh
Reserved
B2
B7
B7 : Osillator Control
logic 0 : 1/2 gain
logic 1 : Full gain
Lock bit
This bit is used to protect the customer's program code in the W78IE54. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
A0 to A7
V
CP
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
A8 to A15
PGM DATA
V
IH
+5V
Programming Configuration
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
A0 to A7
V
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
A8 to A15
PGM DATA
V
IH
+5V
Programming Verification
V
DD
V
DD
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