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參數(shù)資料
| 型號(hào)： | W78ERD2A40PN |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 12/72頁 |
| 文件大?。?/td> | 606K |
| 代理商： | W78ERD2A40PN |
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W78ERD2
- 12 -
Continued
BIT
5
NAME
-
FUNCTION
Reserve
0: Cleared by software.
1: Set automatically when a power-on reset has occurred.
These two bits are general purpose user flags.
These two bits are general purpose user flags.
1: Setting this bit causes the Chip to go into the POWER DOWN mode. In this
mode all the clocks are stopped and program execution is frozen.
1: Setting this bit causes the Chip to go into the IDLE mode. In this mode the clocks
to the CPU are stopped, so program execution is frozen. But the clock to the
serial, timer and interrupt blocks is not stopped, and these blocks continue
operating.
4
POF
3
2
GF1
GF0
1
PD
0
IDL
Timer Control
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON Address: 88h
BIT
NAME
FUNCTION
7
TF1
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared
automatically when the program does a timer 1 interrupt service routine. Software
can also set or clear this bit.
6
TR1
Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or
off.
5
TF0
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared
automatically when the program does a timer 0 interrupt service routine. Software
can also set or clear this bit.
Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or
off.
4
TR0
3
IE1
Interrupt 1 Edge Detect: Set by hardware when an edge/level is detected on INT1.
This bit is cleared by hardware when the service routine is vectored to only if the
interrupt was edge triggered. Otherwise it follows the pin.
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
2
IT1
1
IE0
Interrupt 0 Edge Detect: Set by hardware when an edge/level is detected on INT0 .
This bit is cleared by hardware when the service routine is vectored to only if the
interrupt was edge triggered. Otherwise it follows the pin.
0
IT0
Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
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