參數(shù)資料
型號: W78ERD2A40PL
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝: ROHS COMPLIANT, PLASTIC, LCC-44
文件頁數(shù): 62/76頁
文件大?。?/td> 650K
代理商: W78ERD2A40PL
W78ERD2/W78ERD2A
- 62 -
18.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (T
CP
), and actual parts will usually
experience less than a
±
20 ns variation.
Clock Input Waveform
T
T
XTAL1
F
CH
CL
OP,
T
CP
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Operating Speed
Fop
0
-
40
MHz
1
Clock Period
T
CP
25
-
-
ns
2
Clock High
T
CH
10
-
-
ns
3
Clock Low
T
CL
10
-
-
ns
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
CP
specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
T
AAS
1 T
CP
-
-
-
ns
4
Address Hold from ALE Low
T
AAH
1 T
CP
-
-
-
ns
1, 4
ALE Low to
PSEN
Low
T
APL
1 T
CP
-
-
-
ns
4
PSEN
Low to Data Valid
T
PDA
-
-
2 T
CP
ns
2
Data Hold after
PSEN
High
T
PDH
0
-
1 T
CP
ns
3
Data Float after
PSEN
High
T
PDZ
0
-
1 T
CP
ns
ALE Pulse Width
T
ALW
2 T
CP
-
2 T
CP
-
ns
4
PSEN
Pulse Width
T
PSW
3 T
CP
-
3 T
CP
-
ns
4
Notes
:
1. P0.0
P0.7, P2.0
P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to
PSEN
going high.
4. "
" (due to buffer driving delay and wire loading) is 20 ns.
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