參數(shù)資料
型號(hào)： W78ERD2A40PL
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44
封裝： ROHS COMPLIANT, PLASTIC, LCC-44
文件頁(yè)數(shù)： 35/76頁(yè)
文件大小： 650K
代理商： W78ERD2A40PL
W78ERD2/W78ERD2A
Publication Release Date: February 14, 2007
- 35 -
Revision A10
Mode 3
Mode 3 is used when an extra eight-bit timer is needed, and it has different effects on Timer 0 and
Timer 1.
Timer 0 separates TL0 and TH0 into two separate eight-bit count registers. TL0 uses the Timer 0
control bits
T
C/
, GATE, TR0,
INT0
and TF0 and can count clock cycles (clock / 12 or clock / 6) or
falling edges on pin T0. Meanwhile, TH0 takes over TR1 and TF1 from Timer 1 and can count clock
cycles (clock / 12 or clock / 6).
Mode 3 simply freezes Timer 1, which provides a way to turn it on and off. When Timer 0 is in mode 3,
Timer 1 can still be used in modes 0, 1 and 2, but its flexibility is limited. Timer 1 can still be used as a
timer / counter (or a baud-rate generator for the serial port) and retains the use of GATE and INT1 pin,
but it no longer has control over the overflow flag TF1 and enable bit TR1.
1/6
1/12
T0M = CKCON.3
1
Interrupt
C/T = TMOD.2
0
T0 = P3.4
TH0
TL0
TR0 = TCON.4
GATE = TMOD.3
TR1 = TCON.6
INT0 = P3.2
7
0
TF1
7
0
Interrupt
TF0
0
1
osc
Figure 9-3 Timer/Counter 0 Mode 3
9.2 Timer/Counter 2
Timer 2 is a 16-bit up/down counter equipped with a capture/reload capability. It is configured by the
T2MOD register and controlled by the T2CON register. As with Timers 0 and 1, Timer 2 can count
clock cycles (fosc / 12 or fosc / 6) or the external T2 pin, as selected by
operating modes, each discussed below.
T2
C/
, and there are four
Capture Mode
Capture mode is enabled by setting the
serves as a 16-bit up-counter. When the counter rolls over from FFFFh to 0000h, the TF2 bit is set,
and, if enabled, an interrupt is generated.
RL2
CP/
bit in the T2CON register. In capture mode, Timer 2
If the EXEN2 bit is set, then a negative transition on the T2EX pin captures the value in TL2 and TH2
registers in the RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be
set, which may also generate an interrupt.
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