參數(shù)資料
型號(hào): W78E858
廠(chǎng)商: WINBOND ELECTRONICS CORP
元件分類(lèi): 微控制器/微處理器
英文描述: 8 BIT MICROCONTROLLER
中文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40
封裝: DIP-40
文件頁(yè)數(shù): 7/33頁(yè)
文件大?。?/td> 1186K
代理商: W78E858
W78E858
Publication Release Date: May 5, 2004
- 7 -
Revision A4
6.2 EEPROM
The 128 bytes EEPROM is defined in external data memory space that located in FF80H-FFFFH in
standard 8-bit series. It is accessed the same as auxiliary RAM512 bytes, the ENEEPROM flag in
CHPCON register bit5 is set. Write the page select 03H to MXPSR register, R0 and R1are used as
address pointer. The EEPROM provided byte write, page write mode and software write protection is
used to protect the data lose when power on or noise. They are described as below:
6.2.1 Byte Write Mode
Once a byte write has been started, it will automatically time itself to completion. A BUSY
signal
(MXPSR.7) will be used to detect the end of write operation.
6.2.2 Page Write Mode
The EEPROM is divided into 2 pages and each page contains 64 bytes. The page write allows one to
64 bytes of data to be written into the memory during a single internal programming cycle. Page write
is initiated in the same manner as byte write mode. After the first byte is written, it can then be
followed by one to 63 additional bytes. If a second byte is written within a byte-load cycle time (TBLC)
of 150us, the EEPROM will stay at page load cycle. Additional bytes can then be loaded
consecutively. The page load cycle will be terminated and the internal programming cycle will start if
no additional byte is load within 300us from the last byte be loaded. The address bit6 specify the page
address. All bytes that are
loaded to the buffer must have the same page address. The data for page
write may be loaded in any order, the sequential loading is not required.
6.2.3 Software Protected Data Write
The EEPROM provides a JEDED-approved optional software-protected data write. Once this scheme
is enabled, any write operation requires a series of three-byte program commands (with specific data
to a specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up or power-down. Once enabled, the software data protection will remain
enabled unless the disable commands are issued. To reset the device to unprotected mode, a six-
byte command sequence is required.
The address mapping of the external memory is given as following, if ENAUXRAM or ENEEPROM
flags in CHPCON is not set, the CPU will access external memory instead of the on-chip memory. The
data, address and read/write strobe signal will appear on relative IO port just like standard 80C52.
6.2.4 Command Codes for Software Data Protection Enable/Disable and Software Erase
BYTE
ENABLE WRITE PROTECT
DISABLE WRITE PROTECT
SOFTWARE ERASE
SEQUENCE
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
DATA
0 Write
FFD5H
AAH
FFD5H
AAH
FFD5H
AAH
1 Write
FFAAH
55H
FFAAH
55H
FFAAH
55H
2 Write
FFD5H
A0H
FFD5H
80H
FFD5H
80H
3 Write
-
-
FFD5H
AAH
FFD5H
AAH
4 Write
-
-
FFAAH
55H
FFAAH
55H
5 Write
-
-
FFD5H
20H
FFD5H
10H
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