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參數(shù)資料
| 型號(hào)： | W78E378 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MONITOR MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 18/38頁 |
| 文件大小： | 396K |
| 代理商： | W78E378 |
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Preliminary W78E378/W78C378/W78C374
- 18 -
a) Control Registers
a-1) The Address Registers, S1ADR1, S1ADR2
The SIO1 is equipped with two address registers: S1ADR1 & S1ADR2. The CPU can read from and
write to these two 8-bit, directly addressable SFRs. The content of these registers are irrelevant when
SIO1 is in master modes. In the slave modes, the seven most significant bits must be loaded with the
MCU's own address. The SIO1 hardware will react if either of the addresses is matched.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
-
|------------------------ Own Slave Address -----------------------|
a-2) The Data Register, S1DAT
This register contains a byte of serial data to be transmitted or a byte which has just been received.
The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of
shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag (SI) is set.
Data in S1DAT remains stable as long as SI is set. While data is being shifted out, data on the bus is
simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus,
in the event of lost arbitration, the transition from master transmitter to slave receiver is made with
the correct data in S1DAT.
7
6
5
4
3
2
1
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
|<---------------------------- Shift direction -----------------------------
S1DAT and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the
SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge
bit into S1DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been
shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit (ACK or NACK) is
returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT on the
falling edges of SCL clock pulses, and is shifted into S1DAT on the rising edges of SCL clock pulses.
a-3) The Control Register, S1CON
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the
SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when
a STOP condition is present on the bus. The STO bit is also cleared when ENS1 = "0".
7
6
5
4
3
2
1
0
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
ENS1, the SIO1 Enable Bit
ENS1 = "0": When ENS1 is "0", the SDA and SCL outputs are in a high impedance state. SDA and
SCL input signals are ignored, SIO1 is in the not addressed slave state, and STO bit in S1CON is
forced to "0". No other bits are affected. P3.0 (SDA) and P3.1 (SCL) may be used as open drain I/O
ports.
ENS1 = "1": When ENS1 is "1", SIO1 is enabled. The P3.0 and P3.1 port latches must be set to logic
1.
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| W78C438B | 8-BIT Microcontroller(8位的微控制器) |
| W78C438C40FL | 8-BIT MICROCONTROLLER |
| W78C438C40PL | 8-BIT MICROCONTROLLER |
| W78C458 | 8-BIT EMULATION MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W78E378A10PL | 功能描述:IC MCU 8-BIT 32K FLASH 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:W78 標(biāo)準(zhǔn)包裝:300 系列:78K0R/Ix3 核心處理器:78K/0R 芯體尺寸:16-位 速度:40MHz 連通性:3 線 SIO，I²C，LIN，UART/USART 外圍設(shè)備:DMA，LVD，POR，PWM，WDT 輸入/輸出數(shù):27 程序存儲(chǔ)器容量:16KB（16K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:38-SSOP 包裝:托盤 |
| W78E378P | 制造商:WINBOND 制造商全稱:Winbond 功能描述:MONITOR MICROCONTROLLER |
| W78E51-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| W78E51-24 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| W78E51-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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