參數(shù)資料
型號(hào): W78C374B
廠商: WINBOND ELECTRONICS CORP
英文描述: MONITOR MICROCONTROLLER
中文描述: 顯示器單片機(jī)
文件頁數(shù): 32/38頁
文件大小: 396K
代理商: W78C374B
Preliminary W78E378/W78C378/W78C374
- 32 -
Reset Circuit- Power-low Detector & Watchdog Timer
The reset signals come from the following three sources:
1. External reset input (active low)
2. Power low detect
3. Hardware Watchdog Timer
The power-low detection circuit generates a reset signal once the V
CC
falls below
3.5V
for above 10
μ
S or falls below
1.8V
, and the reset signal is released after V
CC
goes up to
4.3V
.
4.3V
3.8V
1.8V
VCC
Power-low Reset
10uS
The purpose of a watchdog timer is to reset the CPU if the user program fails to reload the watchdog
timer within a reasonable period of time known as the "watchdog interval". The clock source of the
watchdog timer comes from the internal system clock. It can be enabled/disabled by set/clear
WDTEN (bit 5 of CTRL2). For debug purpose, if the WDT reset or power low reset occur, the RESET
pin will be pulled low internally. The pulled-low duration due to WDT reset is about 60/Fosc sec. The
block diagram of the reset circuitry is shown as below.
Watchdog
Timer
Power-low
Supervisor
WDTEN
EN
Reset Logic
R:100K
C:0.01u
External Reset
/RESET
Iol=12mA @Vol=0.45V
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