
Preliminary W78E378/W78C378/W78C374
Publication Release Date: December 1999
- 27 - Revision A1
Sync Processor
Polarity Detector
The H/V polarity is detected automatically and can be known from HPOL bit (HFCOUNTH.7) and
VPOL bit (VFCOUNTH.7).
Fosc
10 MHz
Max. H+V width
Max. V width
(64/Fosc)
×
62 (counter overflow) = 396.8
μ
S
(2048/Fosc)
×
2 = 409.6
μ
S
Sync Separator
The Vsync is separated from the composite sync automatically, without any software effort.
Fosc
10 MHz
Min. V width & Max. H width
(1/Fosc)
×
64 = 6.4
μ
S
Horizontal & Vertical Frequency Counter
There are two 12-bit counters which can count H and V frequency automatically. When VEVENT
(Vsync frequency counter timeout) interrupt happens, the count value values are latched into the
counter registers (HFCOUNTH, HFCOUNTL, VFCOUNTH and VFCOUNTL). And then the S/W may
read the count value (H
COUNT
and V
COUNT
) from the counter registers to calculate the H and V
frequency by the formulas listed below.
V frequency:
The resolution of V frequency counter: V
RESOL
= (1/Fosc)
×
64.
The V frequency: V
FREQ
= 1/(V
COUNT
×
V
RESOL
).
The lowest V frequency can be detected: Fosc ÷ 262144. (38.1Hz @Fosc =10 MHz)
H frequency:
The resolution of H frequency counter: H
RESOL
= (1/Fosc)
÷
8.
The H frequency: H
FREQ
= 1/(H
COUNT
×
H
RESOL
).
The lowest H frequency can be detected: Fosc
÷
512. (19.5 KHz @Fosc = 10 MHz)
Dummy Frequency Generator
The Dummy H and V frequencies are generated for factory burn-in or showing warning message
while there are no input frequency.
(HDUMS1, HDUMS0)
F
dummyH
(0, 0)
(0, 1)
(1, 0)
(1, 1)
Fosc/(8
×
4
×
8)
(8
×
4)/Fosc
Fosc/(8
×
2
×
8)
(8
×
2)/Fosc
Fosc/(8
×
3
×
8)
(8
×
3)/Fosc
Fosc/(8
×
5
×
8)
(8
×
5)/Fosc
Hsync width
VDUMS
F
dummyV
0
1
F
dummyH
/ 512
F
dummyH
/1024
Vsync width
8/ F
dummyH
16/ F
dummyH