參數(shù)資料
型號: W742E
廠商: WINBOND ELECTRONICS CORP
元件分類: 4位微控制器
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
中文描述: 4位單片機(jī)的小型通用紅外遙控器
文件頁數(shù): 24/66頁
文件大?。?/td> 303K
代理商: W742E
Preliminary W742C(E)811
- 24 -
System Clock
Generator
T1
T2
T3
T4
Main Oscillator
XIN1
XOUT1
Sub-oscillator
XIN2
XOUT2
Fosc
Divider 0
SCR : System clock Control Register ( default = 00H )
Bit0
Bit1
Bit2
Bit3
0 : Fosc = Fm
0 : Fm enable
1 : Fm disable
0 : WDT input clock is Fosc/1024
1 : WDT input clock is Fosc/16384
0 : 13 bit
Fm
Fs
enable/disable
STOP
SCR.1
HOLD
SCR.0
LCD Frequency
Selector
F
LCD
Divider 1
INT4
HCF.4
SCR.3(13/12 bit)
1 : 12 bit
Daul clock operation mode:
- SCR.0 =0, Fosc = Fm: SCR.0 = 1, Fosc = Fs
- Flcd = Fs, In STOP mode LCD is turned off.
Figure 5-4 Organization of the dual-clock operation mode
5.11 Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. The WDT can be enabled by mask option code. If the WDT overflows, the chip will be
reset. At initial reset, the input clock of the WDT is F
OSC
/1024. The input clock of the WDT can be
switched to F
OSC
/16384 by setting SCR.2 register. The contents of the WDT can be reset by the
instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows.
A WDT overflow indicates that operation is not under control and the chip will be reset. The WDT overflow
period is about 500 mS when the system clock (F
OSC
) is 32 KHz and WDT clock input is F
OSC
/1024.
The organization of the Divider0 and watchdog timer is shown in Figure 55. The minimum WDT time
interval is 1/(Fosc/16384 x 16) - 1/(Fosc/16384).
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