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Preliminary W742C(E)811
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can be accessed directly or indirectly and the data bank register has to be confirmed firstly. In the
indirect addressing mode, each data bank will be divided into eight pages. The RAM page register has to
be setting when in the indirect accessing RAM. The instructions MOV WRn,@WRq MOV @WRq,WRn
could Read or Write the whole memory in the indirect addressing mode. The RAM address of @WRq
indicates to (DBKRH) * 800H + (DBKRL) * 80H + (RAM page) * 10H + (WRq). The organization of the
data memory is shown in Figure 5-2.
data bank 00
(or Working Registers bank)
5120
address
0000H
:
007FH
0080H
:
00FFH
4 bits
5120 * 4 bits
data bank 01
(or Working Registers bank)
:
:
:
1380H
:
13FFH
data bank 39
00H
:
0FH
10H
1 :
20H
:
2FH
70H
7 :
:
:
1st data RAM page
(or 1st WR page)
2nd data RAM page
(or 2nd WR page)
8th data RAM page
(or 8th WR page)
3rd data RAM page
(or 3rd WR page)
Figure 5-2 Data Memory Organization
The 1st and 2nd data bank (00H to 7FH & 80H to 0FFH) in the data memory can also be used as the
working registers (WR). It is also divided into sixteen pages. Each page contains 16 working registers.
When one page is used as Working Register, the others can be used as the normal data memory. The
WR page register can be switched by executing the MOV WRP,R or MOV WRP,#I instructions. The
data memory can not do the logical operation directly with the immediate data, it has to via the Working
Register.
5.4.2 RAM Page Register (PAGE)
The page register is organized as a 4-bit binary registers. The bit descriptions are as follows:
R/W
R/W
R/W
0
1
2
3
PAGE
Note: R/W means read/write available.
Bit 3 is reserved.
Bit 2, Bit 1, Bit 0 RAM page bits:
000 = Page 0 (00H - 0FH)
001 = Page 1 (10H - 1FH)
010 = Page 2 (20H - 2FH)
011 = Page 3 (30H - 3FH)
100 = Page 4 (40H - 4FH)
101 = Page 5 (50H - 5FH)
110 = Page 6 (60H - 6FH)