參數(shù)資料
型號(hào)： W681513SG
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： 編解碼器
英文描述： A/MU-LAW, PCM CODEC, PDSO20
封裝： 0.300 INCH, ROHS COMPLIANT, SOP-20
文件頁(yè)數(shù)： 3/35頁(yè)
文件大?。?/td> 347K
代理商： W681513SG
W681513
Publication Release Date: October, 2005
- 11 -
Revision A11
held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame
Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125
μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will
become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is
being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync
signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The
internal decision logic will determine whether the next frame sync is a long or short frame sync, based
on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for
two frame sync cycles after every power down state. More detailed timing information can be found in
the interface timing section.
7.4.2. Short Frame Sync
The W681513 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is
HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge
of the bit-clock, the W681513 starts clocking out the data on the PCMT pin, which will also change
from high to low impedance state. The data transmit pin PCMT will go back to the high impedance
state halfway through the LSB. The Short Frame Sync operation of the W681513 is based on an 8-bit
data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after
the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine
whether the next frame sync is a long or short frame sync, based on the previous frame sync pulse.
To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every
power down state. More detailed timing information can be found in the interface timing section.
7.4.3. General Circuit Interface (GCI)
The GCI interface mode is selected when the BCLKR pin is connected to VSS for two or more frame
sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface
consists of 4 pins: FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data
clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK.
The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted
consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is
transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section.
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