參數(shù)資料
型號: W3H64M72E-SBC
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 64M X 72 DDR DRAM, PBGA208
封裝: 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁數(shù): 19/30頁
文件大小: 999K
代理商: W3H64M72E-SBC
W3H64M72E-XSBX
26
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2006
Rev. 2
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC TIMING PARAMETERS
(continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
533Mbs CL4
400Mbs CL3
Unit
Min
Max
Min
Max
Data
DQ hold skew factor
t
QHS
-
400
-
450
ps
DQ output access time from CK/CK#
t
AC
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
t
HZ
tAC(MAX)
ps
DQS Low-Z window from CK/CK#
t
LZ1
tAC(MN)
tAC(MAX)
tAC(MN)
tAC(MAX)
ps
DQ Low-Z window from CK/CK#
t
LZ2
2*tAC(MN)
tAC(MAX)
2*tAC(MN)
tAC(MAX)
ps
DQ and DM input setup time relative to DQS
t
DSa
350
400
ps
t
DHa
350
400
ps
t
DSb
100
150
ps
t
DHb
225
275
ps
DQ and DM input pulse width (for each input)
t
DIPW
0.35
ps
Data hold skew factor
t
QHS
400
450
ps
DQ-DQS hold, DQS to rst DQ to go nonvalid, per access
t
QH
tHP - tQHS
ps
Data valid output window (DVW)
t
DVW
tQH - tDQSQ
ns
Data
Strobe
DQS input high pulse width
t
DQSH
0.35
tCK
DQS input low pulse width
t
DQSL
0.35
tCK
DQS output access time fromCK/CK#
t
DQSCK
-450
+450
-500
+500
ps
DQS falling edge to CK rising - setup time
t
DSS
0.2
tCK
DQS falling edge from CK rising - hold time
t
DSH
0.2
tCK
DQS-DQ skew, DOS to last DQ valid, per group, per access
t
DQSQ
300
350
ps
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
t
WPRES
0
ps
DQS write preamble
t
WPRE
0.25
tCK
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
tCK
Positive DQS latching edge to associated clock edge
t
DQSS
-0.25
0.25
-0.25
0.25
tCK
Write command to rst DQS latching transition
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
tCK
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