參數(shù)資料
型號: W3H32M64EA-400SBI
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 32M X 64 DDR DRAM, PBGA208
封裝: 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁數(shù): 1/28頁
文件大小: 1057K
代理商: W3H32M64EA-400SBI
W3H32M64EA-XSBX
ADVANCED*
White Electronic Designs
White Electronic Designs Corp. reserves the right to change products or specications without notice.
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
February 2010 2010 White Electronic Designs Corp. All rights reserved
Rev. 0
32M x 64 DDR2 SDRAM Single-Rank 208 PBGA MCP
FEATURES
Data rate = 667, 533, 400 Mb/s
Package:
208 Plastic Ball Grid Array (PBGA), 16 x 20mm
1.0mm pitch
Supply Voltage = 1.8V ± 0.1V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 3, 4 or 5
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Commercial, Industrial and Military Temperature
Ranges
Organized as 32M x 64
Weight: W3H32M64EA-XSBX - 2.5 grams typical
BENEFITS
62% Space savings vs. FBGA
Reduced part count
42% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradeable to 64M x 64 density (contact factory
for information)
*This product is under development, is not qualied or characterized and is subject
to change or cancellation without notice.
Area
4 x 209mm2 = 836mm2
320mm2
62%
4 x 90 balls = 360 balls
208 Balls
42%
S
A
V
I
N
G
S
I/O
Count
W3H32M64EA-XSBX
CSP Approach (mm)
90
FBGA
11.0
19.0
90
FBGA
11.0
90
FBGA
11.0
90
FBGA
11.0
FIGURE 1 – DENSITY COMPARISONS
20
16
White
Electronic
Designs
W3H32M64EA-XSBX
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