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參數(shù)資料
| 型號(hào)： | W3H128M72ER-667SBI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 0.5 ns, PBGA255 |
| 封裝： | 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255 |
| 文件頁數(shù)： | 1/34頁 |
| 文件大小： | 1028K |
| 代理商： | W3H128M72ER-667SBI |
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W3H128M72ER-XNBX
PRELIMINARY*
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2009
Rev. 6
White Electronic Designs Corp. reserves the right to change products or specications without notice.
23
Area
5 x 161mm2 + 1 x 74mm2 = 879mm2
483mm2
45%
5 x 84 balls + 1 x 96 balls = 516 balls
255 Balls
51%
128M x 72 REGISTERED DDR2 SDRAM 255 PBGA
FEATURES
Data rate = 667, 533, 400 Mb/s
Package:
255 Plastic Ball Grid Array (PBGA), 23 x 21mm2
1.27mm pitch
Core Supply Voltage = 1.8V
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 4, 5 or 6
CK/CK# Termination options available
0 ohm, 20 ohm
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Commercial, Industrial and Military Temperature
Ranges
1GByte Organized as 128M x 72
Weight: W3H128M72ER-XNBX - 4 grams max
BENEFITS
45% Space savings vs. FBGA
Reduced part count
51% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
* This product is under development, is not fully qualied or characterized and is
subject to change without notice.
S
A
V
I
N
G
S
I/O
Count
W3H128M72ER-XNBX
CSP Approach (mm)
21
FIGURE 1 – DENSITY COMPARISONS
White Electronic Designs
W3H128M72ER-XSBX
96
FBGA
13.5
84
FBGA
11.5
84
FBGA
11.5
84
FBGA
11.5
84
FBGA
11.5
5.5
84
FBGA
11.5
14.0
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