參數(shù)資料
型號(hào)： W3H128M72ER-533SBM
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： DRAM
英文描述： 128M X 72 DDR DRAM, 0.5 ns, PBGA255
封裝： 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255
文件頁(yè)數(shù)： 3/34頁(yè)
文件大?。?/td> 1028K
代理商： W3H128M72ER-533SBM
W3H128M72ER-XNBX
11
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2009
Rev. 6
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
on die termination (ODT) (RTT), posted AL, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specied time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecied operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
DLL
Posted CAS#
out
A9
A7 A6 A5 A4 A3
A8
A2
A1 A0
Extended Mode
Register (Ex)
Address Bus
97
6
5
4
3
82
1
0
A10
A12
A11
BA0
BA1
10
11
12
13
0
14
Poste d CA S# A dditive Laten cy (AL)
0
1
2
3
4
Reserved
E3
0
1
0
1
0
1
0
1
E4
0
1
0
1
E5
0
1
0
1
DLL Ena ble
Enable (Normal)
Disable (Test/Debug)
E0
15
0
1
RDQ S Ena ble
No
Yes
E11
OCD Program
A13
A14
ODS
RTT
DQS#
0
1
DQ S# Ena ble
Enable
Disable
E10
RDQS
Rtt (nominal)
RTT disabled
75
Ω
150
Ω
50
Ω
E2
0
1
0
1
E6
0
1
0
1
Outputs
Enabled
Disabled
E12
0
1
0
1
Mo de Regi ster Set
Mode register set (MRS)
Extended mode register (EMRS)
Extended mode register (EMRS2)
Extended mode register (EMRS3)
E16
0
0
1
E15
MRS
OCD Operation
OCD not supported 1
Reserved
OCD default state
1
E7
0
1
0
1
E8
0
1
0
1
E9
0
1
0
1
Output Drive Strength
E1
Full strength (18
Ω target)
Reduced strength (40
Ω target)
RTT
E17
0
0
BA2
16
17
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is nished, as detailed in the
initialization procedure.
2.. E14 (A14) is not used on this device.
相關(guān)PDF資料
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W3H128M72ER-667SBC 128M X 72 DDR DRAM, 0.5 ns, PBGA255
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