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參數(shù)資料
| 型號(hào)： | W3EG7266S202BD4IF |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.8 ns, DMA200 |
| 封裝： | LEAD FREE, SO-DIMM-200 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | W3EG7266S202BD4IF |
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W3EG7266S-AD4
-BD4
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October 2004
Rev. 7
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C
≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V ± 0.1V (200MHz)
Parameter
Symbol Conditions
DDR400@
CL=3
DDR333@
CL=2.5
DDR266@
CL=2, 2.5
DDR200@
CL=2
Units
Max
Operating Current
IDD0
One device bank; Active - Precharge;
(MIN); DQ,DM and DQS inputs
changing once per clock cycle;
Address and control inputs changing
once every two cycles. TRC=TRC(MIN);
TCK=TCK
1670
1445
mA
Operating Current
IDD1
One device bank; Active-
Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
1940
1715
mA
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down
mode; TCK=TCK(MIN); CKE=(low)
45
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
TCK=TCK(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
770
680
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down
mode; TCK(MIN); CKE=(low)
405
315
mA
Active Standby
Current
IDD3N
CS# = High; CKE = High; One
device bank; Active-Precharge;
TRC=TRAS(MAX); TCK=TCK(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per clock
cycle.
815
725
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst;
One device bank active;Address
andcontrol inputs changing once
per clock cycle; TCK=TCK(MIN); IOUT
= 0mA.
1985
1760
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; TCK=TCK(MIN); DQ,DM and
DQS inputs changing twice per clock
cycle.
2030
1850
1670
mA
Auto Refresh Current
IDD5
TRC=TRC(MIN)
3360
2885
mA
Self Refresh Current
IDD6
CKE ≤ 0.2V
320
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with TRC=TRC
(MIN); TCK=TCK(MIN); Address and
control inputs change only during
Active Read or Write commands
4325
3875
mA
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