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參數(shù)資料
| 型號： | W3EG6433S262BD4 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SODIMM-200 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 342K |
| 代理商： | W3EG6433S262BD4 |
9
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3EG6433S-AD4
-BD4
May 2005
Rev. 1
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Notes
1.
All voltages referenced to VSS.
2.
Tests for AC timing, IDD, and electrical AC and DC characteristics may
be conducted at nominal reference/supply voltage levels, but the related
specications and device operation are guaranteed for the full voltage range
specied.
3.
Outputs measured with equivalent load:
Output
(V
(VOUT
OUT
)
Reference
Point
50Ω
VTT
TT
30pF
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point
for CK/CK#), and parameter specications are guaranteed for the specied
AC input levels under normal use conditions. The mini-mum slew rate for the
input signals used to test the device is 1V/ns in the range between VIL(AC) and
VIH(AC).
5.
The AC and DC input level specications are as dened in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6.
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF
may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for AC noise. This measurement is
to be taken at the nearest VREF bypass capacitor.
7.
VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track
variations in the DC level of VREF.
8.
IDD is dependent on output loading and cycle rates. Specied values are obtained
with mini-mum cycle time at CL = 2 for 262, 263, and 202, CL = 2.5 for 335 and
265 with the outputs open.
9.
Enables on-chip refresh and address counters.
10.
IDD specications are tested after the device is properly initialized, and is
averaged at the dened cycle rate.
11.
This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS,
f = 100 MHz, = 25°C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) TA = 0.2V. DM
input is grouped with I/O pins, reecting the fact that they are matched in loading.
12.
For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rate
is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each
100mV/ns reduction in slew rate from 500mV/ns, while tIH is unaffected. If slew
rate exceeds 4.5 V/ns, functionality is uncertain. For 335, slew rates must be ≥
0.5 V/ns.
13.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point
at which CK and CK# cross; the input reference level for signals other than
CK/CK# is VREF.
14.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the
period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.
15.
The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
16.
tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specic voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
17.
The intent of the Don’t Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above VIH DC (MIN) then it must not transition low (below
VIH DC) prior to tDQSH (MIN).
18.
This is not a device limit. The device will operate with a negative value, but
system performance could be degraded due to bus turnaround.
19.
It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
20.
MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets
the minimum absolute Value for the respective parameter. tRAS (MAX) for IDD
measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
21.
The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125μs.
However, an AUTO REFRESH command must be asserted at least once every
70.3μs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
22.
The valid data window is derived by achieving other specications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly
porportional with the clock duty cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond
which functionality is uncertain. Figure 8, Derating Data Valid Window, shows
derating curves for duty cycles ranging between 50/50 and 45/55.
23.
Each byte lane has a corresponding DQS.
24.
This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e.,
during standby).
25.
To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target
AC level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.After the AC target level is reached,
continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
26.
JEDEC species CK and CK# input slew rate must be ≥ 1V/ns (2V/ns
differentially).
27.
DQ and DM input slew rates must not deviate from DQS by more than 10
percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew
rate. If slew rate exceeds 4V/ns, functionality is uncertain. For 335, slew rates
must be ≥ 0.5 V/ns.
28.
VCC must not vary more than 4 percent if CKE is not active while any bank is
active.
29.
The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to
vary by the same amount.
30.
tHP min is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively during bank active.
31.
READs and WRITEs with auto precharge are not allowed to be issued until
tRAS(MIN) can be satised prior to the internal precharge command being issued.
32.
Any positive glitch must be less than 1/3 of the clock and not more than +400mV
or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock
cycle and not exceed either -300mV or 2.2V, whichever is more positive.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG6433S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S263D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S263JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| W3EG6433S265AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6433S265BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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