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參數資料
| 型號： | W3EG2128M64ETSR335JD3MF |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 256M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | LEAD FREE, DIMM-184 |
| 文件頁數： | 10/13頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W3EG2128M64ETSR335JD3MF |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
April 2005
Rev. 0
W3EG2128M64ETSR-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and register power
Parameter
Symbol
Conditions
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC=tRC
(MIN); tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two cycles.
2720
2520
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst
= 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
3000
2800
mA
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power-down mode; tCK=tCK
(MIN); CKE=(low)
160
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; tCK=tCK (MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ,
DQS and DM.
1350
1270
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down mode; tCK
(MIN); CKE=(low)
560
480
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle.
1110
1030
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.
3200
2960
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK=tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
3280
3040
rnA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
4140
3980
mA
Self Refresh Current
IDD6
CKE
≤ 0.2V
475
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN);
Address and control inputs change only during
Active Read or Write commands.
5640
5240
mA
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