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參數(shù)資料
| 型號： | W3E32M64S-200BC |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 813K |
| 代理商： | W3E32M64S-200BC |
W3E32M64S -X BX
8
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2006
Rev. 3
COMMAND
READ
NOP
NOP
NOP
CL = 2.5
DON'T CARE
TRANSITIONING DATA
DQ
DQS
T0
T1
T2
T2n
T3
T3n
COMMAND
READ
NOP
NOP
NOP
CL = 2
DQ
DQS
CLK
CLK
T0
T1
T2
T2n
T3
T3n
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DATA
CLK
CLK
FIGURE 4 – CAS LATENCY
FIGURE 5 – EXTENDED MODE
REGISTER DEFINITION
DLL
E
na
bl
e
D
i
sa
bl
e
D
LL
DS
A
9
A
7
A
6
A
5
A
4
A
3
A
8
A
2
A
1
A
0
Ex
tended
Mode
Reg
i
ster
(Ex)
Address
Bus
O
p
erat
i
ng
Mode
A
10
A
11
11
01
BA
0
BA
1
E0
0
1
Drive Strength
N
orma
l
Reduced
E1
0
1
Operating Mode
Reser
v
ed
Reser
v
ed
E1, E0
V
a
li
d
-
E12
0
-
E10
0
-
E9
0
-
E8
0
-
E7
0
-
E6
0
-
E5
0
-
E4
0
-
E3
0
-
A
12
E11
0
-
1
. E
1
4
and
E
13
must
b
e
"
0
,
1
"
to
se
l
ect
the
Ex
tended
Mode
Reg
i
ster
(v
s
.
the
b
ase
Mode
Reg
i
ster
)
2
. T
he
Q
F
C
f
unct
i
on
i
s
not
su
pp
orted
.
E2
0
-
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
pa am e ers. Input A10 de er mines wheth er one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, in puts BA0, BA1 select the
bank. Oth er wise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be ac i vat ed pri or to any READ or WRITE commands
being is sued to that bank. A PRECHARGE com mand will
be treat ed as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
pro cess of precharging.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same in di vid u al-bank PRECHARGE function de scribed
above, but with out re quir ng an explicit command. This is
ac com plished by using A10 to enable AUTO PRECHARGE
in conjunction with a spe ci
fi
c READ or WRITE command.
A precharge of the bank/row that is ad dressed with the
READ or WRITE com mand is au o mat cal y performed
upon com ple ion of the READ or WRITE burst. AUTO
PRECHARGE is non persistent in that it is either en abled
or dis abled for each in di vid u al READ or WRITE command.
The device sup ports concurrent auto precharge if the
com mand to the oth er bank does not in er upt the data
transfer to the current bank.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was is sued at the earliest possible
time, without violating t
RAS
(MIN).The user must not is sue
an oth er com mand to the same bank until the precharge
time (t
RP
) is com plet ed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3E32M64S-200BI | 32Mx64 DDR SDRAM |
| W3E32M64S-200BM | 32Mx64 DDR SDRAM |
| W3E32M64S-250BC | 32Mx64 DDR SDRAM |
| W3E32M64S-250BI | 32Mx64 DDR SDRAM |
| W3E32M64S-250BM | 32Mx64 DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E32M64S-200BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-200BM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M64S-200SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-200SBI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-200SBM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 208 PBGA, MIL-TEMP. - Bulk |
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