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參數(shù)資料
| 型號： | W3E32M64S-200BC |
| 英文描述： | 32Mx64 DDR SDRAM |
| 中文描述： | 32Mx64 DDR內(nèi)存 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 813K |
| 代理商： | W3E32M64S-200BC |
W3E32M64S -X BX
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
July 2006
Rev. 3
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to de
fi
ne the speci
fi
c mode of
op er a ion of the DDR SDRAM. This de
fi
nition includes the
selection of a burst length, a burst type, a CAS latency,
and an op er at ng mode, as shown in Figure 3. The Mode
Reg s er is programmed via the MODE REG S TER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored in or ma ion until it is pro grammed again or
the device loses power. (Ex cept for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Reg s er must be load ed (reloaded) when all banks are
idle and no bursts are in progress, and the con rol er must
wait the spec
fi
ed time be ore ini i at ng the sub se quent
op er a ion. Vi o at ng either of these re quire ments will result
in un spec
fi
ed operation.
Mode register bits A0-A2 specify the burst length, A3 spec
fi
es
the type of burst (sequential or in er eaved), A4-A6 spec y the
CAS latency, and A7-A12 specify the op er at ng mode.
BURST LENGTH
Read and write ac cess es to the DDR SDRAM are burst
ori ent ed, with the burst length being programmable,
as shown in Fig ure 3. The burst length determines
the maximum num ber of column lo ca ions that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 lo ca ions are avail able for both the
sequential and the in er eaved burst types.
Reserved states should not be used, as unknown op er a ion
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
col umns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
mean ng that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most signi
fi
cant
column address for a given con
fi
guration); and by A3-Ai
when the burst length is set to eight. The remaining (least
sig ni
fi
cant) ad dress bit(s) is (are) used to select the starting
lo ca ion within the block. The pro grammed burst length
ap plies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be pro grammed to be
either se quen ial or interleaved; this is re erred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is de er mined by
the burst length, the burst type and the start ng column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the reg s ra ion of a READ command and the avail abil y
of the
fi
rst bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the op er at ng fre quen cies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
re quired, JEDEC speci
fi
cations recommend when a LOAD
MODE REG S TER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to se ect nor mal op er at ng mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3E32M64S-200BI | 32Mx64 DDR SDRAM |
| W3E32M64S-200BM | 32Mx64 DDR SDRAM |
| W3E32M64S-250BC | 32Mx64 DDR SDRAM |
| W3E32M64S-250BI | 32Mx64 DDR SDRAM |
| W3E32M64S-250BM | 32Mx64 DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3E32M64S-200BI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-200BM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 219 PBGA, MIL-TEMP. - Bulk |
| W3E32M64S-200SBC | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 208 PBGA, COMMERCIAL TEMP. - Bulk |
| W3E32M64S-200SBI | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
| W3E32M64S-200SBM | 制造商:Microsemi Corporation 功能描述:32M X 64 DDR, 2.5V, 200 MHZ, 208 PBGA, MIL-TEMP. - Bulk |
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