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參數(shù)資料
| 型號： | W3E232M16S-250STC |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W3E232M16S-250STC |
W3E232M16S-XSTX
14
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS DDR400
-40°C ≤ TA ≤ +85°C; VCCQ = +2.5V ±0.2V, VCC = +2.6V ±0.1V Notes: 1-5, 14-17. 33
AC Characteristics
DDR400
Unit
Notes
Parameter
Symbol
Min
Max
Access window of DQs from CK/CK#
tAC
-0.70
+0.70
ns
CK high-level width
tCH
0.45
0.55
tCK
30
CK low-level width
tCL
0.45
0.55
tCK
30
Clock cycle time
CL = 3
tCK (3)
5
7.5
ns
51
CL = 2.5
tCK (2.5)
7.5
13
ns
45, 51
CL = 2
tCK (2)
-
ns
45, 51
DQ and DM input hold time relative to DQS
tDH
0.40
ns
26, 51
DQ and DM input setup time relative to DQS
tDS
0.40
ns
26, 51
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
31
Access window of DQS from CK/CK#
tDQSCK
-0.60
+0.60
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS–DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.40
ns
25, 26
WRITE command to rst DQS latching transition
tDQSS
0.72
1.28
tCK
DQS falling edge to CK rising – setup time
tDSS
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH,tCL
ns
34
Data-out high-impedance window from CK/CK#
tHZ
+0.70
ns
18, 42
Data-out low-impedance window from CK/CK#
tLZ
-0.7
ns
18, 42
Address and control input hold time (slew rate ≤0.5V/ns)
tIHF
0.60
ns
14
Address and control setup time (slew rate ≤0.5V/ns)
tISF
0.60
ns
14
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
ns
DQ–DQS hold, DQS to rst DQ to go non-valid, per access
tQH
tHP-tQHS
ns
25, 26
Data hold skew factor
tQHS
0.50
ns
ACTIVE to PRECHARGE command
tRAS
40
70,000
ns
35
ACTIVE to READ with auto precharge command
tRAP
15
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
55
ns
AUTO REFRESH command period
tRFC
70
ns
49
ACTIVE to READ or WRITE delay
tRCD
15
ns
PRECHARGE command period
tRP
15
ns
DQS read preamble
tRPRE
0.9
1.1
tCK
43
DQS read postamble
tRPST
0.4
0.6
tCK
43
ACTIVE bank a to ACTIVE bank b command
tRRD
10
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
20, 21
DQS write postamble
tWPST
0.4
0.6
tCK
19
Write recovery time
tWR
15
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3E232M16S-250STCG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-250STI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-250STIG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-266STC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
| W3E232M16S-266STCG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM |
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