參數(shù)資料
型號: W311
英文描述: Clocks and Buffers
中文描述: 時(shí)鐘和緩沖器
文件頁數(shù): 1/19頁
文件大?。?/td> 602K
代理商: W311
FTG for VIA Pro-266 DDR Chipset
W311
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
July 3, 2003
1W311
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
System frequency synthesizer for VIA Pro-2000
Programmable clock output frequency with less than
1 MHz increment
Integrated fail-safe Watchdog Timer for system
recovery
Automatically switch to HW selected or SW
programmed clock frequency when Watchdog Timer
time-out
Capable of generate system RESET after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength for CPU and PCI output
clocks
Programmable output skew between CPU, AGP and PCI
Block Diagram
Supports Intel Celeron and Pentium III class pro-
cessor
Three copies of CPU output
Nine copies of PCI output
One 48-MHz output for USB
One 24-MHz or 48-MHz output for SIO
Two buffered reference outputs
Three copies of APIC output
Supports frequencies up to 200 MHz
SMBus interface for programming
Power management control inputs
Available in 48-pin SSOP
Key Specifications
CPU Cycle-to-Cycle Jitter:...........................................250 ps
CPU to CPU Output Skew:..........................................175 ps
PCI Cycle to Cycle Jitter:.............................................500 ps
PCI to PCI Output Skew:.............................................500 ps
Intel, Pentium, and Celeron are registered trademarks of Intel Corporation.
Pin Configuration
Note:
1.
Signals marked with ‘*’ have internal pull-up resistors.
[1]
VDD_REF
REF0
REF1/FS4
OSC
PLL Ref Freq
DIV
PLL 1
X2
X1
VDD_PCI
CStop
PCI1:8
48MHz/FS3
24_48MHz/FS2
PLL2
÷6, ÷8,
÷10, ÷12
PWR_DWN#
VDD_48 MHz
SMBus
Logic
SSCLK
CPU1:3
RST#
VDD_REF
GND_REF
X1
X2
VDD_48 MHz
FS3*/48 MHz
FS2*/24_48 MHz
GND_48 MHz
PCI_F
PCI1
PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
*FS1
*FS0
AGP0
VDD_AGP
W
REF0
REF1/FS4*
VDD_APIC
APIC0
APIC1
GND_APIC
APIC2
VDD_CPU
GND_CPU
CPU1
CPU2
VDD_CPU
GND_CPU
CPU3
CPU_STOP#*
PCI_STOP#*
RST#
VDD_CORE
GND_CORE
SDATA
SCLK
AGP2
AGP1
GND_AGP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
÷2
CStop
PCI_STOP#
PCI_F
APIC0:1
VDD_AGP
AGP0:2
DIV
FS0:1
CPU_STOP#
VDD_CPU
VDD_APIC
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