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參數(shù)資料
| 型號： | W27E02P-70 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 256K X 8 EEPROM 5V, 70 ns, PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 268K |
| 代理商： | W27E02P-70 |
Preliminary W27E02
256K
× 8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: April 14, 2005
- 1 -
Revision A2
1. GENERAL DESCRIPTION
The W27E02 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 262,144
× 8 bits. It requires only one supply in the range of 5.0V ± 10% in
normal read mode. The W27E02 provides an electrical chip erase function.
2. FEATURES
Single power supply voltage: 5.0V
±10%
High speed access time: 70/90 nS (max.)
Read operating current: 30 mA (max.)
Erase/Programming operating current:
30 mA (max.)
Standby current: 20
A (max.)
+12V erase/programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 32-pin 600 mil DIP, 32-lead
PLCC and 32-lead STSOP
3. PIN CONFIGURATIONS
A6
A5
A4
A3
A2
A1
A0
Q0
5
6
7
8
9
10
11
12
13
Q
1
Q
2
Q
4
Q
5
Q
6
1
4
4 32 1 3
2
3
1
3
0
A14
A13
A8
A9
#OE
A11
Q7
29
28
27
26
25
24
23
22
21
32-lead PLCC
V
s
1
5
1
6
1
7
1
8
1
9
2
0
A
1
V
D
#CE
A10
A
1
5
A
1
6
Q
3
A7
A
1
2
V
p
#
P
G
M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A2
A1
A0
Q0
Q1
Q2
#OE
A10
#CE
Q7
Q6
Q5
Q4
Q3
32-lead STSOP
A15
A12
A7
A6
A5
A4
#PGM
A14
A13
A8
VDD
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A17
V SS
VPP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Q0
A0
A2
A3
A4
A5
A6
A7
A12
A15
A16
A1
Vpp
Vss
Q2
Q1
30
31
32
25
26
27
28
29
20
21
22
23
24
19
18
17
Q5
#OE
A10
Q7
Q6
A13
A8
A9
A11
#PGM
A17
A14
Q3
Q4
#CE
V DD
32-pin
PDIP
7
4. BLOCK DIAGRAM
V
Vss
DD
VPP
CONTROL
OUTPUT
BUFFER
DECODER
CORE
ARRAY
Q0
Q7
.
#CE
#OE
A0
.
A17
#PGM
5. PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0
A17
Address Inputs
Q0
Q7
Data Inputs/Outputs
#CE
Chip Enable
#OE
Output Enable
#PGM
Program Enable
VPP
Program/Erase Supply Voltage
VDD
Power Supply
Vss
Ground
NC
No Connection
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