參數(shù)資料
型號(hào)： W19B320STB9F
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： TFBGA-48
文件頁(yè)數(shù)： 50/52頁(yè)
文件大小： 1869K
代理商： W19B320STB9F
W19B(L)320ST/B
Publication Release Date: March 23, 2004
- 7 -
Revision A2
Please note that the #WP/ACC pin can not be at VHH for operations excepts accelerated
programming; otherwise, the device will be damaged. In addition, the #WP/ACC pin can not be left
floating; otherwise, an unconnected inconsistent behavior will occur.
Autoselect Functions
When the system writes the autoselect command sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the internal register (which is separate from the
memory array) on DQ0–DQ7. The standard read cycle timings is applied in this mode. Please refer to
the Autoselect Mode and Autoselect Command Sequence sections for more information.
6.1.4 Standby Mode
When the system is not reading or writing to the device, the device will be in a standby mode. In this
mode, current consumption is greatly reduced, and the outputs are in the high impedance state,
independent from the #OE input.
When the
#CE and #RESET pins are both held at VDD ± 0.3V, the device enters into the CMOS standby
mode (note that this is a more restricted voltage range than VIH.) When #CE and #RESET are held at VIH,
but not within VDD
0.3V, the device will be in the standby mode, but the standby current will be greater.
The device requires standard access time (t
±
CE) for read access when the device is in either of these standby
modes, before it is ready to read data.
When the device is deselected during erasing or programming, the device initiates active current until
the operation is completed.
6.1.5 Automatic Sleep Mode
The automatic sleep mode minimizes device's energy consumption. When addresses remain stable
for tACC +30 nS, the device will enable this mode automatically. The automatic sleep mode is
independent from the #CE, #WE, and #OE control signals. Standard address access timings provide
new data when addresses are changed. In sleep mode, output data is latched and always available to
the system.
6.1.6 #RESET: Hardware Reset Pin
The #RESET pin provides a hardware method to reset the device to reading array data. When the
#RESET pin is set to low for at least a period of tRP, the device will immediately terminate every
operations in progress, tri-states all output pins, and ignores all read/write commands for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data mode.
To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to
accept another command sequence.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at VSS
0.3V, the
device initiates the CMOS standby current (I
±
CC4). If #RESET is held at VIL but not within VSS ± 0.3V,
the standby current will be greater.
The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the
device, enabling the system to read the boot-up firmware from the device.
If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until
the internal reset operation is complete. If #RESET is asserted when a program or erase operation is
not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during
Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH.
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