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參數(shù)資料
| 型號(hào)： | W134MH |
| 英文描述： | Miscellaneous Clock Generator |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大小： | 244K |
| 代理商： | W134MH |
W137
7
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF)
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
Description
Period
High Time
Low Time
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate
Measured from 2.4V to 0.4V
Duty Cycle
Measured on rising and falling edge at 1.5V
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
Output Skew
Measured on rising edge at 1.5V
CPU to PCI Clock
Offset
edge at 1.5V. CPU leads PCI output.
Frequency Stabiliza-
tion from Power-up
(cold start)
stabilization.
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
CPU = 66.6/100 MHz
Min.
Typ.
30
12.0
12.0
1
1
45
Unit
ns
ns
ns
V/ns
V/ns
%
ps
Max.
4
4
55
250
t
SK
t
O
500
4.0
ps
ns
Covers all CPU/PCI outputs. Measured on rising
1.5
f
ST
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
3
ms
Z
o
20
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
f
t
R
t
F
t
D
f
ST
Description
Test Condition/Comments
Determined by crystal oscillator frequency
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100 MHz
Min.
Typ.
14.318
0.5
0.5
45
Unit
MHz
V/ns
V/ns
%
ms
Max.
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
2
2
55
3
Z
o
AC Output Impedance
25
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