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參數(shù)資料
| 型號： | VV5430C001 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Monochrome Analog Output CMOS Image Sensors |
| 中文描述： | 單色模擬輸出CMOS圖像傳感器 |
| 文件頁數(shù)： | 25/33頁 |
| 文件大?。?/td> | 256K |
| 代理商： | VV5430C001 |
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VV5430
Write to Camera
CD5430F-A
25/33
Setup Code_1
Header Code = 0001
Valid data bits: 11
The code_1 setup register is used to select different basic operating modes:
Note
:
Decreasing the system clock rate proportionately increases sensor sensitivity (by increasing exposure time), but
also decreases frame frequency. System Clock must be x1 for standard CCIR or EIA framing.
Bit
Function
Default
Comment
0
Normal/Backlit
0
Selects between normal and backlit exposure modes. The
power-on default is normal mode. See Exposure Control
for full description
Selects between a linear (LIN=1) or gamma corrected
video signal on AVO. The power-on default is gamma cor-
rected.
Allows automatic gain control to be inhibited. The current
gain value selected is frozen. With AGC=0 a new gain
value can be written to the gain register via the serial inter-
face (header code 0101).
Allows automatic black calibration to be inhibited.
Allows automatic exposure control to be inhibited. The cur-
rent exposure value selected is frozen. Note that if auto-
matic exposure control is inhibited then automatic gain
control is also disabled. With AEC=0 a new exposure
value can be selected by writing to the coarse and fine
exposure registers via the serial interface (header codes
0011 & 0100).
Shuffles the read out of the horizontal shift register. Even
columns read out together then odd columns.
Shuffles the readout of the vertical shift register. Even
lines read out together then odd lines.
Requests a re-calibration of the black level while bit is low.
System clock division: (see Note)
0,0=1; 0,1=÷2; 1,0=÷4; 1,1=÷8
1
Linear Correction enable
0
2
Auto gain control enable
1
3
4
Inhibit black calibration
Auto exposure control enable
0
1
5
Horizontal shuffle enable
0
6
Vertical shuffle enable
0
7
8
9
10
11
Force black calibration
Clock divisor DIV0
Clock divisor DIV1
Internal Register
Not used
1
0
0
0
0
This bit must be set to 0 for correct sensor operation
Table 15 : Set-up code_1
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