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參數(shù)資料
| 型號(hào)： | VT83205S1X |
| 廠商： | Vaishali Semiconductor |
| 英文描述： | 3.3V Low Phase Noise VCXO Voltage-Controlled Crystal Oscillator and PLL Clock Synthesizer |
| 中文描述： | 3.3V的低相位噪聲壓控電壓控制晶體振蕩器和PLL時(shí)鐘合成器 |
| 文件頁(yè)數(shù)： | 4/4頁(yè) |
| 文件大小： | 79K |
| 代理商： | VT83205S1X |
VT83205
2001-03-08
Page
4
MDST-0001-01
www.vaishali.com
Vaishali Semiconductor 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Table 6. DC Electrical Characteristics
T
A
= 0
°
C to +70
°
C, V
DD
= 3.15 V to 3.45 V
Parameter
Output High Voltage, V
OH
Condition
I
OH
=-25mA
Min
2.4
Typ
(1)
Max
Units
V
Output Low Voltage, V
OL
I
OL
=25mA
0.4
V
Operating Supply Current, I
DD
No Load
38
mA
Short Circuit Current
Each output
±85
mA
Input Capacitance
S2:0, OE
7
pF
Note
:
1. Typical values are at V
DD
= 3.3V and 25°C
Table 7. AC Electrical Characteristics
T
A
= 0
°
C to +70
°
C, V
DD
= 3.15 V to 3.45 V
Symbol
Fosc
Input Crystal Frequency
Tr
Output Clock Rise Time
tf
Output Clock Fall Time
t
od
Output Clock Duty Cycle
tpZL, tpZH
Enable Time. OE to CLK
tpLZ, tpHZ
Disable Time. OE to CLK
t
jit
(pk-pk)
Maximum Absolute Jitter
(Peak to Peak)
Phase Noise, relative to carrier
Output pullability
Parameter
Condition
0.8 to 2.0V
2.0 to 0.8V
At V
DD
/2
C
L
= 50pf
C
L
= 50pf
Min
10
40
Typ
5
4
±100
Max
14.318
1.5
1.5
60
6.5
5.5
Units
MHz
ns
ns
%
ns
ns
ps
10 KHz offset
0V <
V
IN
<
3V
-115
dBc/Hz
ppm
±100
Note:
1. Typical values are at V
DD
= 3.3V and 25°C
Figure 3. External Crystal Connection Block Diagram
Ordering Information
Part Number
Marking
VT83205Q
VT83205Q
VT83205QX
VT83205Q
VT83205S1
VT83205S1
VT83205S1X
VT83205S1
VT83205/D
Shipping/Packaging
Tubes
Tape & Reel
Tubes
Tape & Reel
Die
No. of Pins
16
16
16
16
Package
QSOP
QSOP
SOIC
SOIC
Temperature
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
X2
X1
33pF
X2
33pF
C
X1
XTAL OSC
XTAL OSC
PLL
CLOCK
GEN
OE
20pF
(C
X2
)
20pF
C
X1
External Crystal
Load Capacitors
10-14MHz
Pullable Crystal
Clk 1
Clk
2
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