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參數(shù)資料
| 型號(hào)： | VT83205S1X |
| 廠商： | Vaishali Semiconductor |
| 英文描述： | 3.3V Low Phase Noise VCXO Voltage-Controlled Crystal Oscillator and PLL Clock Synthesizer |
| 中文描述： | 3.3V的低相位噪聲壓控電壓控制晶體振蕩器和PLL時(shí)鐘合成器 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 79K |
| 代理商： | VT83205S1X |
2001-03-08
Page
1
MDST-0001-01
www.vaishali.com
Vaishali Semiconductor 1300 White Oaks Road, Ste. 200 Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Applications
=
Telecom switching
=
Set-top boxes
=
=
HDTV
MPEG Video clock source
General Description
The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer.
The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz,
30pF (pull range of 200 ppm) crystal input, in order to produce either one or two output clocks. A 0 to 3V
control signal is used to fine tune the output clock frequency in the ±100ppm range. Select inputs SO:S2
are used for frequency and output selection.
Features
=
3.3V supply operation
=
Packaged in 16-pin SOIC & QSOP packages.
=
Replaces separate VCXO and multiplier
=
Uses inexpensive pullable crystal
=
On-chip VCXO with 200 ppm pull range (±100
ppm)
5V-tolerant control inputs
Zero ppm synthesis error in both clocks
=
=
Figure 1. Functional Block Diagram
VT83205
3.3V Low Phase Noise VCXO
(Voltage-Controlled Crystal Oscillator)
and PLL Clock Synthesizer
CLK1
CLK2
VDD1
VDD2
X2
Load Cap Control
Low
Phase
Noise
PLL
Output
Buffer
Output
Buffer
osc
Load
Caps
OE
10-14 MHz
Pullable
Crystal
S2:S0
VIN
X1
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