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參數(shù)資料
| 型號： | VSP3100 |
| 英文描述： | 14-Bit, 10MHz CCD/CIS SIGNAL PROCESSOR |
| 中文描述： | 14位，10MHz的防治荒漠化公約/ CIS信號處理器 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 195K |
| 代理商： | VSP3100 |
14
VSP3100
DIGITAL OUTPUTS
The digital outputs of the VSP3100 are designed to be
compatible with both high-speed TTL and CMOS logic
families. The driver stage of the digital outputs is supplied
through a separate supply pin, V
DRV
(pin 41), which is not
connected to the analog supply pins (V
CC
). By adjusting the
voltage on V
DRV
, the digital output levels will vary respec-
tively. Thus, it is possible to operate the VSP3100 on a +5V
analog supply while interfacing the digital outputs to 3V
logic. It is recommended to keep the capacitive loading on
the data lines as low as possible (typically less than 15pF).
Larger capacitive loads demanding higher charging current
surges can feed back to the analog portion of the VSP3100
and influence the performance. If necessary, external buff-
ers or latches may be used, providing the added benefit of
isolating the VSP3100 from any digital noise activities on
the bus, coupling back high-frequency noise. In addition,
resistors in series with each data line may help minimize the
surge current. Their use depends on the capacitive loading
seen by the converter. As the output levels change from low
to high and high to low, values in the range of 100
to 200
will limit the instantaneous current the output stage has to
provide for recharging the parasitic capacitances.
PROGRAMMABLE GAIN AMPLIFIER
VSP3100 has one Programmable Gain Amplifier (PGA),
and it is inserted between the CDSs and the 3:1 MUX. The
PGA is controlled by a 5-bit of Gain Register and each
channel (Red, Green, and Blue) has its own Gain Register.
The gain varies from 1 to 4.44 (0dB to 13dB), and the curve
has log characteristics. Gain Register Code all “0” corre-
sponds to minimum gain, and Code all “1” corresponds to
maximum gain.
The transfer function of the PGA is:
Gain = 4/(4 – 0.1 x)
where, x is the integer representation of the 5-bit PGA gain
register.
Figure 1 shows the PGA transfer function plot.
INPUT CLAMP
The input clamp should be used for 1-channel and 3-channel
CCD mode, and it will be enabled when both CLP and CK1
are set to HIGH.
Bit Clamp:
the input clamp is always enabled.
Line Clamp:
enables during the dummy pixel interval at
every horizontal line, and disables during the effective pixel
interval.
Generally, “Bit Clamp” is used for many scanner applica-
tions, however, “Line Clamp” is used instead of “Bit Clamp”
when the clamp noise is impressive.
CHOOSING THE AC INPUT COUPLING
CAPACITORS
The purpose of the Input Coupling Capacitor is to isolate the
DC offset of the CCD array from affecting the VSP3100
input circuitry. The internal clamping circuitry is used to
restore the necessary DC bias to make the VSP3100 input
circuitry functional. Internal clamp voltage, V
CLAMP
, is set
when both the CLP pin and CK1 are set high. V
CLAMP
changes depending on the value of V
REF
. V
CLAMP
is 2.5V if
V
REF
is set to 1V (D1 of the Configuration Register set to
“0”), and V
CLAMP
is 3V if V
REF
is set to 1.5V (D1 of the
Configuration Register set to “1”).
FIGURE 1. PGA Transfer Plot.
PGA TRANSFER FUNCTION
PGA Gain Setting
5
10
15
20
25
31
0
G
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
PGA TRANSFER FUNCTION
PGA Gain Setting
5
10
15
20
25
31
0
G
14
12
10
8
6
4
2
0
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PDF描述 |
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| VSP3100Y | 14-Bit, 10MHz CCD/CIS SIGNAL PROCESSOR |
| VSP3200 | CCD SIGNAL PROCESSOR FOR SCANNER APPLICATIONS |
| VSP3200Y | CCD SIGNAL PROCESSOR FOR SCANNER APPLICATIONS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP3100Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 14-Bit 10Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP3100Y/2K | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 14-Bit 10Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP3100Y/2KG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 14-Bit 10Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP3100YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 14-Bit 10Msps CCD/ CIS Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP3200 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR FOR SCANNER APPLICATIONS |
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