參數(shù)資料
型號: VSP2260Y
英文描述: CCD SIGNAL PROCESSOR for DIGITAL CAMERAS
中文描述: CCD信號處理器的數(shù)碼相機(jī)
文件頁數(shù): 10/13頁
文件大?。?/td> 221K
代理商: VSP2260Y
VSP2260
SBMS010
10
REGISTER DEFINITIONS
C[0]
Operation Mode, Normal/Stand-By
Serial Interface and Registers are always active, independently from the operation mode.
C0 = Operation Mode for the entire chip except the serial interface and registers.
(C0 = 0 “Active”; C0 = 1 “Stand-by”)
G[9:0]
The Characteristics of PGA Gain
(refer to Figure 2)
O[3:0]
Programmable OB Clamp Level
(refer to Table I)
P[2:0]
Clock Polarity
P0 = Polarity for CLPDM
P1 = for CLPOB
P2 = for SHP/SHD
(P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”)
(P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”)
(P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”)
Immediately after power ON, these values are Unknown. The appropriate value must be set by using the serial interface, or reset
to the default value by strobing the RESET pin.
Default values are:
G[9:0] = 0010000000
O[3:0] = 1000
P[2:0] = 000
Normal Operation Mode
PGA Gain = 0dB
OB Clamp Level = 32LSB
CLPDM, CLPOB, SHP/SHD are all “Active LOW”
(1)
NOTE: (1) The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value).
REGISTERS
TEST
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Configuration
PGA Gain
OB Clamp Level
Clock Polarity
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
0
0
0
0
x
x
x
x
x
0
0
0
0
x
x
x
x
x
0
0
0
0
0
0
0
0
0
C0
G0
O0
P0
x
x
x
x
x
G9
0
0
x
x
x
x
x
G8
0
0
x
x
x
x
x
G7
0
0
x
x
x
x
x
G6
0
0
x
x
x
x
x
G5
0
0
x
x
x
x
x
G4
0
0
x
x
x
x
x
G3
O3
0
x
x
x
x
x
G2
O2
P2
x
x
x
x
x
G1
O1
P1
x
x
x
x
x
x = Don
t Care.
TABLE II. Serial Interface Data Format.
MSB
LSB
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