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參數(shù)資料
| 型號： | VSP2212Y |
| 英文描述： | CCD SIGNAL PROCESSOR For Digital Cameras |
| 中文描述： | CCD信號處理器的數(shù)碼相機(jī) |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 125K |
| 代理商： | VSP2212Y |
8
VSP2212
HIGH PERFORMANCE ANALOG-TO-DIGITAL
CONVERTER (ADC)
The Analog-to-Digital Converter (ADC) utilizes a fully
differential and pipelined architecture. This ADC is well
suited for low-voltage operations, low-power consumption
requirements, and high-speed applications. It guarantees
12-bit resolution of output data with no missing code.
The VSP2212 includes a reference voltage generator for the
ADC. REFP (Positive Reference, pin 38), REFN (Negative
Reference, pin 39), and CM (Common-Mode Voltage,
pin 37) should be bypassed to ground with a 0.1
μ
F ceramic
capacitor, and should not be used elsewhere in the system;
they affect the stability of these reference levels, and cause
ADC performance degradation. Note that these are analog
output pins.
PROGRAMMABLE GAIN AMPLIFIER (PGA)
Figure 2 shows the characteristics of the PGA gain. The
PGA provides a gain range of –6dB to +42dB, which is
linear in dB. The gain is controlled by a digital code with
10-bit resolution, and can be set through the serial interface
(refer to the “Serial Interface” section for more detail).
The default value of the gain control code is 128 (PGA
Gain = 0dB). However, immediately after power on, this
value is “Unknown”. For this reason, the appropriate value
must be set by using the serial interface, or reset to the
default value by the RESET pin.
OPTICAL BLACK (OB) LEVEL CLAMP LOOP
During the effective pixel interval, the reference level of the
CCD output signal is clamped to the OB level by the OB
level clamp loop. To determine the loop time constant, an
off-chip capacitor is required, and should be connected to
COB (pin 28). Time constant T is given in the following
equation:
T = C/(16384 I
min
)
Where C is the capacitor value connected to COB, I
min
is the
minimum current (0.15
μ
A) of the control DAC in the OB
level clamp loop, and 0.15
μ
A is equivalent to 1LSB of the
DAC output current. When C is 0.1
μ
F, the time constant T
is 40.7
μ
s.
Additionally, the slew rate SR is given the following equa-
tion:
SR = I
max
/C
Where C is the capacitor value connected to COB, I
max
is the
maximum current (153
μ
A) of the control DAC in the OB
level clamp loop, and 153
μ
A is equivalent to 1023LSB of
the DAC output current.
Generally, OB level clampling at high speed causes “Clamp
Noise” (or “White Streak Noise”), however, the noise will
decrease by increasing C. On the other hand, an increased C
requires a much longer time to restore from Stand-By mode,
or right after power on. Therefore, we consider 0.1
μ
F to
0.22
μ
F a reasonable value for C. However, it depends on the
application environment; we recommend making careful
adjustments using trial-and-error.
The “OB clamp level” (the pedestal level) is programmable
through the serial interface (refer to the “Serial Interface”
section for more detail). Table I shows the relationship
between input code and the OB clamp level.
To extract the video information correctly, the CCD signal
must be referenced to a well-established Optical Black (OB)
level. The VSP2212 has an auto-calibration loop to establish
the OB level using the optical black pixels output from the
CCD imager. The input signal level of the OB pixels is
identified as the real “OB level”, and the loop should be
closed during this period while CLPOB is active.
FIGURE 2. Characteristics of PGA Gain.
Input Code for Gain Control (0 to 1023)
G
50
40
30
20
10
0
–10
0
1
2
3
4
5
6
7
8
9
1
1
INPUT CODE
OB CLAMP LEVEL, LSBs OF 12 BITS
0000
2 LSB
0001
18 LSB
0010
34 LSB
0011
50 LSB
0100
66 LSB
0101
82 LSB
0110
98 LSB
0111
114 LSB
1000 (Default)
130 LSB
1001
146 LSB
1010
162 LSB
1011
178 LSB
1100
194 LSB
1101
210 LSB
1110
226 LSB
1111
242 LSB
TABLE I. Programmable OB Clamp Level.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2212Y/2K | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20 Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2212Y/2KG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20 Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP2212YG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 12-Bit 20 Msps Signal Processor RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| VSP-2220 | 制造商:QUEST TECHNOLOGY 功能描述:2 WAY SPLITTER 1 GHZ |
| VSP2221GPLR | 制造商:Texas Instruments 功能描述: |
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