- 您現(xiàn)在的位置：買賣IC網 > PDF目錄361748 > VSP2080 CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS PDF資料下載
參數(shù)資料
| 型號： | VSP2080 |
| 英文描述： | CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號前端的數(shù)碼相機高端處理器 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 80K |
| 代理商： | VSP2080 |
6
VSP2080
DIFFERENCE AMPLIFIER
The correlated double sampler function is completed when
the output of the data and reference channel are sent to the
difference amplifier where the signals are subtracted. In
addition to providing the difference function, the difference
amplifier amplifies the signal by a factor of 2 which helps
to improve the overall signal-to-noise ratio. The difference
amplifier also generates a differential signal to drive the
voltage-controlled attenuator.
INPUT CLAMP
The output from the CCD array is capacitively coupled to the
VSP2080. To prevent shifts in the DC level from taking place
due to varying input duty cycles, the input capacitor is
clamped during the dummy pixel interval by the REFCK
signal. A P-channel transistor is used for this input clamp
switch to be able to allow a 2V negative change at the input
that would bring the signal below ground by 1V. Under
typical conditions, the black level at the input to the VSP2080
is at 1V.
DUMMY PIXEL AUTO-ZERO LOOP
The output from the data and reference channel is processed
by the previously mentioned difference amplifier. The dif-
ferential output from the difference amplifier is sent to both
the voltage-controlled logarithmic attenuator and to an error
amplifier. The error amplifier amplifies and feeds a signal to
the difference amplifier to drive the offset measured at the
output of the difference amplifier to zero. A block diagram
of this circuit is shown in Figure 3. This error amplifier
serves the purpose of reducing the offset of the CDS to avoid
a large offset from being amplified by the output amplifier.
The effective time constant of this loop is given by:
where R is 10k
, C is an external capacitor connected to
CCD R (pin 14), A is the gain of the error amplifier with a
value of 50, and D is the duty cycle of the time that the dummy
pixel auto-zero loop is in operation. The duty cycle (D) must
be considered as the loop operates in a sampled mode. Opera-
tion of the dummy auto-zero loop is activated by the DUMC
signal that happens once during each horizontal line interval.
TIMING
The REFCK and DATCK signals are used to operate the
CDS as previously explained. The input digital timing sig-
nals REFCK, DATCK, DUMC and OB are capable of being
driven from either 3V or 5V logic levels.
VOLTAGE-CONTROLLED ATTENUATOR
To maximize the dynamic range of the VSP2080, a voltage-
controlled attenuator is included with a control range from
0dB to –34dB. The gain control has a logarithmic relation-
ship between the control voltage and the attenuation. The
attenuator processes a differential signal from the difference
amplifier to improve linearity and to reject both power supply
and common-mode noise. The output from the attenuator is
amplified by 28dB prior to being applied to the A/D. A typical
gain control characteristic of the VSP2080 is shown in the
typical performance curve, “Gain Control Characteristics”.
BLACK LEVEL AUTO-ZERO LOOP
The black level auto-zero loop amplifies the difference
between the output of the output amplifier and a reference
signal during the dummy pixel interval. This difference
signal is amplified and fed back into the output amplifier to
correct the offset. In doing so, the output level of the entire
CCD channel can be controlled to be approximately –FS +
31mV under zero signal conditions. The black level auto-
zero loop is activated by the OB timing signal. Figure 4
shows a block diagram of the black level auto-zero loop. The
loop time constant is given by:
where C is the external filter capacitance applied to C (pin 4),
G
M
is .001 Siemens (inverse ohm) and D is the duty cycle
of the time that the black level auto-zero loop is in operation.
The duty cycle (D) must be considered as the loop operates
in a sampled mode. Operation of the black level auto-zero
loop is activated by the OB signal that happens once during
each horizontal line interval.
FIGURE 3. Simplified Block Diagram of Dummy Pixel
Loop.
FIGURE 4. Simplified Block Diagram of Optical Black
Level Auto-Zero Loop.
T
C
G
D
M
=
DUMC
To VCA
CDS
Error
Amplifier
A
CCD D
CCD R
R
C
EXT
OUT
1.03 REF IN
Error
Amplifier
Output Amplifier
G
M
From
VCA
C
C
EXT
OB
T
R C
A D
=
相關PDF資料 |
PDF描述 |
|---|---|
| VSP2080T | CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
| VSP2101 | CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2101Y | CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2210 | CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2210Y | CCD SIGNAL PROCESSOR For Digital Cameras |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2080T | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
| VSP2100 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2100Y | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2101 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2101Y | 功能描述:視頻模擬/數(shù)字化轉換器集成電路 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。