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參數(shù)資料
| 型號： | VSP2080 |
| 英文描述： | CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
| 中文描述： | CCD信號前端的數(shù)碼相機高端處理器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 80K |
| 代理商： | VSP2080 |
5
VSP2080
THEORY OF OPERATION
The VSP2080 contains all of the key features associated with
the processing of analog signals in a CCD video camera or
digital still camera. Figure 1 shows a simplified block
diagram of the VSP2080. The output from the CCD array is
first clamped to an internal reference of +1V. This sets the
proper signal range for the input of the Correlated Double
Sampler (CDS). The CDS operates at at gain of 2 and
provides a differential output. Its output drives a voltage-
controlled attenuator with a logarithmic control characteris-
tic. An output amplifier drives this signal to external cir-
cuitry and sets the proper black level for the ADS900 A/D
converter.
CORRELATED DOUBLE SAMPLER (CDS)
The CDS removes low frequency noise from the output of
the image sensor. Refer to Figure 2 which shows a block
diagram of the CDS. The output from the CCD array is
sampled during the reference interval as well as during the
data interval. Noise that is present at the input and is of a
period greater than the pixel interval will be eliminated by
subtraction.
The VSP2080 employs a three track-and-hold correlated
double sampler architecture. Track/Hold 2 samples the CCD
noise during the reference interval as driven by the REFCK
signal. Track/Hold 3 resamples this level at the same time
that Track/Hold 1 samples the video information as driven
by the DATCK signal. This is done to remove large tran-
sients from Track/Hold 2 that result from a portion of the
reset transient being present during the acquisition time of
this track-and-hold. The output of Track/Hold 2 is buffered
by a voltage follower.
FIGURE 2. Simplified Block Diagram of Correlated Double Sampler.
FIGURE 1. Simplified Block Diagram of VSP2080.
VCA
CDS
Clamp
REFCK DATCK
Black Level
Auto-Zero
Loop
Dummy
Feedback
Loop
OB
Gain Control
DUMC
Output
Amplifier
Analog
Output
CCD D
CCD
OUT
C
EXT
Data Sampling Channel
Reference Sampling
Channel
T/H1
T/H3
T/H2
1V
DUMC REFCK
DATCK
To VCA
CCD D
CCD
OUT
C
EXT
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PDF描述 |
|---|---|
| VSP2080T | CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
| VSP2101 | CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2101Y | CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2210 | CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2210Y | CCD SIGNAL PROCESSOR For Digital Cameras |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| VSP2080T | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL FRONT-END PROCESSOR FOR DIGITAL CAMERAS |
| VSP2100 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2100Y | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2101 | 制造商:BB 制造商全稱:BB 功能描述:CCD SIGNAL PROCESSOR For Digital Cameras |
| VSP2101Y | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 27 Msps w/10-Bit On-Chip DAC RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結構: 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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