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參數(shù)資料
| 型號(hào)： | VSC880TY |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 19/28頁 |
| 文件大小： | 289K |
| 代理商： | VSC880TY |
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VITESSE
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
G52191-0, Rev 4.2
01/05/01
Page 19
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
3.4 Transmitter Operation
If CMODE is HIGH and the force IDLE register is set LOW, the transmitter sends data words from the switch
fabric. If the force IDLE register is set HIGH, IDLE words are transmitted. At the end of the cell clock period, bits
B[1:0] in all IDLE words are set to 11 to embed the cell clock marker. For data words, user defined overhead bits are
passed on to the destination as is.
3.5 Delaying The Cell Clock
If out-of-band messaging is used between the port cards and the switch card, there will be a phase offset between
the cell clock (CCLK) on the switch card, and the transmit cell clock (RTM/TCLK) on the port card. A cell clock
delay value can be programmed into the control register CDEL[3:0] to set the time the switch is configured after
receiving a cell clock. This adds 1-14 word clocks worth of delay between CCLK input to the switch chip and the cell
clock sent to the transceivers from the switch chip. In this way, the transmit cell clock (RTM/TCLK) on the
transceivers can be aligned to the cell clock at the switch chip (CCLK). For a typical system design where the
transceiver is less then 20
”
from the switch chip, the default value of 5 can be used. See Application Note 32 for more
details.
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