參數(shù)資料
型號(hào)： VSC880TY
英文描述： Interface IC
中文描述： 接口IC
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 289K
代理商： VSC880TY
VITESSE
Data Sheet
VSC880
High Performance 16x16
Serial Crosspoint Switch
Page 10
G52191-0, Rev 4.2
01/05/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
FI[15:0]Force IDLE register, bit 0 is channel 0 etc
RESY[15:0]Resynch register, bit 0 is channel 0 etc
OE[15:0]Output enable register, bit 0 is channel 0 etc
LPBK[15:0]Facility loopback register, bit 0 is channel 0 etc
1.5 Parallel CPU Interface
There is a parallel 8 bit CPU interface on the VSC880 that can be used to read and write the status and control
registers described above. This is an asynchronous interface that was design to operate with many common micro
controllers that are available. The functional timing diagrams for a write and a read are shown in the following
figures. Timing information can be found in the AC Characteristics section of this data sheet.
Figure 2:
CPU Interface Functional Write Cycle Timing
Figure 3:
CPU Interface Functional Read Cycle Timing
1.6 Parallel Configuration Interface
In addition to reading and writing the switch configuration using the CPU interface as described above, the entire
switch matrix can be reprogrammed in 4 word clocks by setting the CEN signal LOW. If CEN is set LOW, the
parallel interface DATA[15:0] contains a 16 bit switch configuration input port, the inputs FI[3:0] load the FI bits and
the WEN signal becomes a programming signal as shown in the figure below. It takes 4 word clocks to load all 64 bits
of switch configuration data and 16 FI bits into holding registers. All data transfer timing is relative to REFCLK.
After data has been loaded, and if CCLK is HIGH, all 80 bits of data are strobed into the switch matrix and FI control
logic. Otherwise, the configuration information is stored in holding registers until the next CCLK pulse strobes it in.
Since the CCLK signal is delayed internally in the switch, it can be asserted as early as the WEN signal pulse to
strobe in the configuration information.
ADDR
CWEN
CDATA
CSEL
Valid Data
Valid Address
ADDR
CWEN
CDATA
CSEL
Valid Data
Valid Address
Hi-Z
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