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參數(shù)資料
| 型號： | VSC8021 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
| 中文描述： | 容量高達(dá)2.5GB / s的SONET的兼容8位/解復(fù)用器芯片組 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大小： | 220K |
| 代理商： | VSC8021 |
VITESSE
Data Sheet
VSC8021/VSC8022
2.5Gb/s SONET-Compatible
8-Bit MUX/DEMUX Chipset
Page 6
G52028-0, Rev 4.1
05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Table 2: VSC8022 Demultiplexer AC Characteristics
NOTE: (1) If t
C
changes, all the remaining parameters change as indicated by the equations.
DC Characteristics
Table 3: Low Speed ECL Inputs and Outputs
(
Over recommended operating range with internal V
REF,
V
CC
= GND, output load = 50
to -2.0V)
Note: Differential ECL output pins must be terminated identically.
Table 4: High-Speed Inputs and Outputs
(Over recommended operating conditions, V
CC
= GND, Output load = 50
to -2.0V)
NOTES: (1) A reference generator is built in to each high-speed input, and these inputs are designed to be AC-coupled.
(2) If a high-speed input is used single-ended, a 150pF capacitor must be connected between the unused high-speed or comple-
ment input and the power supply (V
TT
).
(3) Differential high-speed outputs must be terminated identically.
Parameter
Description
Min
Typ
Max
Units
Conditions
t
C
t
D
t
BD
t
DFP
Clock period
(1)
400
ps
BYTE clock period (t
D
= t
C
x 8) (framed)
BYTE clock output to valid data
3.2
ns
0.5
1.0
2.0
ns
FP rising edge from parallel data output
change from A1 to A2 (t
DFP
= t
D
)
FP pulse width (t
PFP
= t
D
)
OOFN falling edge before A1 chan
ges to A2 (t
OOFN
= t
D
x 4)
OOFN pulse width (t
OOFNPW
= t
D
)
Serial data phase timing margin with respect
to high-speed clock:
Phase Margin =
3.2
ns
t
PFP
3.2
ns
t
OOFN
12.8
ns
t
OOFNPW
3.2
ns
Phase
Margin
135
180
degrees
Parameter
Description
Min
Typ
Max
Units
Conditions
V
OH
V
OL
Output HIGH voltage
Output LOW voltage
-1020
V
TT
-700
-1620
mV
mV
V
IN
= V
IH
(max) or V
IL
(min)
V
IN
= V
IH
(max) or V
IL
(min)
Guaranteed HIGH signal for
all inputs
Guaranteed LOW signal for
all inputs
Output load 50
to V
TT
V
IH
Input HIGH voltage
-1150
-600
mV
V
IL
Input LOW voltage
V
TT
-1500
mV
V
OUT
Output voltage swing
0.8
1.0
1.4
V
Parameter
Description
Min
Typ
Max
Units
Conditions
V
IN
V
OH
V
OL
V
OUT(DATA)
V
OUT(clk)
Input voltage swing
Output HIGH voltage
Output LOW voltage
Output voltage swing for data
Output voltage swing for clock
0.8
1.0
-0.9
-1.8
0.8
0.7
1.2
V
V
V
V
V
AC-coupled
Output load, 50
to -2.0V
Output load, 50
to -2.0V
Output load, 50
to -2.0V
Output load, 50
to -2.0V
0.6
0.6
1.2
1.2
1
t
-------------------
t
H
+
C
–
360
°
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| VSC8022FC | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
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