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參數(shù)資料
| 型號： | VSC8021 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
| 中文描述： | 容量高達2.5GB / s的SONET的兼容8位/解復用器芯片組 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大小： | 220K |
| 代理商： | VSC8021 |
VITESSE
G52028-0, Rev 4.1
05/25/01
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano Camarillo, CA 93012
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Data Sheet
VSC8021/VSC8022
8-Bit MUX/DEMUX Chipset
2.5Gb/s SONET-Compatible
Features
Serial Data Rates up to 2.5Gb/s
Functional Description
The VSC8021 and VSC8022 are high-speed SONET interface devices capable of handling serial data at
rates up to 2.5Gb/s. These devices can be used for STS-3 through STS-48 SONET applications.
These products are fabricated in gallium arsenide using the Vitesse H-GaAs
E/D MESFET process which
achieves high-speed and low power dissipation. These products are packaged in a ceramic 52-pin leaded
ceramic chip carrier.
VSC8021
The VSC8021 contains an 8:1 multiplexer and a self-positioning timer. The 8:1 multiplexer accepts 8 paral-
lel differential ECL data inputs (D1-D8, D1N-D8N) at rates up to 312.5Mb/s and multiplexes them into a serial
differential bit stream output (DO, DON) at rates up to 2.5Gb/s.
The internal timing of the VSC8021 is built around the high-speed clock (up to 2.5GHz) delivered onto the
chip through a differential input (CLKI, CLKIN). This signal is subsequently echoed at the high-speed differen-
tial output (CO, CON).
The parallel data inputs are clocked to on-chip input registers with an externally supplied differential ECL
input (BYCLK, BYCLKN) operating at the same rate as the data inputs. An internal byte clock, which is a
divide-by-8 version of the high-speed clock, is used to transfer the data to a set of buffer registers. This internal
byte clock is brought off chip at the ECL output CLK8, CLK8N.
Internal circuitry monitors the internal and external byte clocks and generates an ERR signal if a timing
violation is detected. This signal can be gated to the SYNC input which is edge sensitive high. An active SYNC
input allows the VSC8021 timing to shift, positioning it properly against the external byte clock, CLK8,
CLK8N. When a CLK8 timing switch is made, normal data flow will be invalid for 1 byte.
There are two clock inputs, CLKI and BYCLK, going into the VSC8021. These two clocks serve as timing
references for different parts of the VSC8021. The BYCLK is used to trigger the input registers for the parallel
data inputs, while the CLKI is used to trigger the high-speed serial output register as well as some of the timing
circuitry for the parallel to serial conversion. Furthermore, in order to make this part easy to use, the user is not
required to assume a known phase relationship between CLKI and the BYCLK.
Differential or Single-Ended Inputs and Outputs
Low Power Dissipation: 2.3W (Typ Per Chip)
Standard ECL Power Supplies:
V
EE
= -5.2V, V
TT
= -2.0V
Available in Commercial (0
°
C to +70
°
C) or Industrial
(-40
°
C to +85
°
C) Temperature Ranges
Proven E/D Mode GaAs Technology
52-Pin Leaded Ceramic Chip Carrier
Parallel Data Rates up to 312.5Mb/s
ECL 100K Compatible Parallel Data I/Os
Divide-by-8 Clock for Synchronization of
Parallel Data to Interfacing Chips
SONET Frame Recovery Circuitry
(VSC8022)
Compatible with STS-3 to STS-48
SONET Applications
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSC8021FC | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
| VSC8021FI | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
| VSC8022 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
| VSC8022FC | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
| VSC8022FI | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset |
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