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參數(shù)資料
| 型號(hào)： | VSC7125 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | Rotary Switch; Contact Current Max:1.5A; No. of Poles:4; No. of Switch Positions:11; Indexing:30 ; No. of Decks:4; Switch Terminals:Solder Lug; Circuitry:SPDT; Mounting Type:Panel; Switch Features:30 degrees Indexing RoHS Compliant: Yes |
| 中文描述： | 1.0625 Gbits / sec的光纖通道收發(fā)器 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 123K |
| 代理商： | VSC7125 |
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VITESSE
SEMICONDUCTOR CORPORATION
Page 5
4/23/98
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
VITESSE
Data Sheet
VSC7125
1.0625 Gbits/sec Fibre
Channel Transceiver
G52121-0, Rev. 4.1
Figure 4: Transmit Timing Waveforms
AC Characteristics
Table 1: Transmit AC Characteristics
Parameters
Description
Min
Max
Units
Conditions
T
1
T0:9 Setup time to the rising
edge of REFCLK
1.5
—
ns.
Measured between the valid
data level of T0:9 to the 1.4V
point of REFCLK
T
2
T0:9 hold time after the
rising edge of REFCLK
1.0
—
ns.
T
SDR
,T
SDF
TX+/TX- rise and fall time
—
300
ps.
20% to 80%, 75 Ohm load to
Vss, Tested on a sample basis
T
LAT
Latency from rising edge of
REFCLK to T0 appearing on
TX+/TX-
11bc - 1ns
ns.
bc = Bit clocks
ns = Nano second
Transmitter Output Jitter Allocation
T
rj
Serial data output random
jitter (RMS)
Serial data output
deterministic jitter (p-p)
—
20
ps.
RMS, tested on a sample basis
(refer to Figure 8)
Peak to peak, tested on a sample
basis (refer to Figure 8)
T
DJ
—
100
ps.
Data Valid
T0:9
T
1
10 Bit Data
T
2
REFCLK
Data Valid
Data Valid
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| VSC7125QN | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:1.0625 Gbits/sec Fibre Channel Transceiver |
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| VSC7126 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:1.0625 Gbits/sec Fibre Channel Transceiver |
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